Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 34 Motherboard Design Guidelines
Technologies, Inc.
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2.3.2.5 Host CPU Clock and SDRAM Clock Signals
Layout recommendations for host clocks and SDRAM clocks for Slot-1 and Socket-370 CPUs are shown in Figure 2-26 and 2-27
respectively. 22 ohm and 10 ohm series terminations are recommended for all host clocks and all SDRAM clocks respectively. It
is also recommended that bypass capacitors be added to all clock signals on the clock synthesizer side. Different values of series
terminations and bypass capacitors are needed for a better clock transmission and alignment on the final PCB layout. In other
words, it is best to observe the actual clock waveform and experimentally determine the optimal values for series termination and
bypass capacitors. For clock alignment considerations, trace lengths of all clocks should match the longest one.
System
Clock
Synthesizer
Slot-1 CPU
CPUCLK
SDCLK_F
HCLK
SDCLKIN
DIMM1
VT82C694X
DIMM3
DIMM2
SDCLK0
SDCLK9
SDCLK10
SDCLK11
SDCLK8
SDCLK7
SDCLK6
SDCLK5
SDCLK4
SDCLK3
SDCLK2
SDCLK1
0 ~ 33
ohm
10 ~ 33 pF
L
CPU
L
CPU
+ 3"
L
SD
+ 4.5"
L
SD
L
DOUT
(as short as possible)
0 ~ 33
ohm
10 ~ 33 pF
DCLKWR
DCLKO
10 ~ 33 pF
DIMM4
SDCLK13
SDCLK14
SDCLK15
SDCLK12
CK0
CK3
CK2
CK1
CK0
CK3
CK2
CK1
CK0
CK3
CK2
CK1
CK0
CK3
CK2
CK1
HCLK
(near the chip)
L
SD
L
SD
L
SD
(near the chip)
Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System