Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 32 Motherboard Design Guidelines
Technologies, Inc.
We ConnectWe Connect
2.3.2.3 Clock Routing Considerations
Clock routing guidelines are listed below:
• The recommended range of a clock trace width is between 15 mils and 20 mils.
• The minimum space between one clock trace and adjacent clock traces is 15 mils. The minimum space from one segment
of a clock trace to other segments of the same clock trace is two times of the clock width. That is, more space is needed
from one clock trace to others or its own trace to avoid signal coupling (see Figure 2-23).
• Clock traces should be parallel to their reference ground planes. That is, a clock trace should be right beneath or on top of
its reference ground plane (see Figure 2-24).
• Series terminations (damping resistors) are needed for all clock signals (typically 10 ohms to 33 ohms). When two loads
are driven by one clock signal, the series termination layout is shown in Figure 2-25. When multiple loads (more than
two) are applied, a clock buffer solution is preferred.
• Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically 20 mils to 50
mils) are preferred.
• No clock traces on the internal layer if a six-layer board is used.
Clock
Synthesizer
15 mils
Two times of the width
of the clock segment
Clock trace
Clock
Segment
Figure 2-23. Clock Trace Spacing Guidelines
Another
ground
plane
Relative
ground
plane
Clock trace
Relative
ground
plane
Clock trace
Another
ground
plane
RECOMMENDED NOT RECOMMENDED
Figure 2-24. Effect of Ground Plane to a Clock Signal
Clock Source
Damping resistors
Clock Load
Clock Load
In equal length In equal length
Figure 2-25. Series Termination for Multiple Clock Loads