Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A

Preliminary Revision 0.5, November 19, 1999 31 Motherboard Design Guidelines

Technologies, Inc.

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2.3.2.2 Clocking Scheme

The 17 (66 / 100 / 133MHz) SDRAM clocks are generated from a clock buffer inside the system clock synthesizer. They are

controlled by the SDRAM clock output (DCLKO) provided by the Apollo Pro133A North Bridge. The VT82C694X (North

Bridge) has a built-in de-skew Phase Lock Loop (PLL) circuitry for optimal skew control within and between clocking regions.

For more details, refer to Figure 2-22.

VT82C694X (North Bridge)

DCLKO

DCLK

Clock

Synthesizers

DRAM Clock

De-skew PLL

HCLK

CCLK

GCLK

DCLK

DCLKI

External Clock

Synthesizer

with SDRAM

Clock Buffer

DIMM1

DIMM4 DIMM2

4 SDCLKs to

each DIMM

HCLK: External Host clock - 66MHz / 100MHz / 133MHz

CCLK: Internal Host clock - 66MHz / 100MHz / 133MHz

DCLK: Memory (SDRAM) clock - 66MHz / 100MHz / 133MHz

GCLK: AGP clock - 66MHz only

GCLK4XI: AGP 4X clock - 266MHz

DIMM3

GCLKO

AGP Clock

De-skew PLL

GCLK

GCLKI

22 ohm

GCLKO

to AGP slot

GCLK4XI

Figure 2-22. Apollo Pro133A Chip Clocking Scheme