Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A

Preliminary Revision 0.5, November 19, 1999 30 Motherboard Design Guidelines

Technologies, Inc.

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2.3.2 Apollo Pro133A Clock Layout Recommendations

2.3.2.1 Clock Requirements

The requirements of the system clock synthesizer for an Apollo Pro133A based system design are listed in Table 2-7.

Table 2-7. Apollo Pro133A Clock Synthesizer Requirements

Clock Signal Type Frequency (MHz) Quantity Connections

CPU Clock 66/75/83/95/

100/124/133

3 Connect to CPU (1), Apollo Pro133A (1) and ITP Debug Port (1)

SDRAM Clock 66/100/133 17 Connect to four SDRAM slots (16) and Apollo Pro133A (1)

SDRAM Clock In 66/100/133 1 Connect to Apollo Pro133A (1)

PCI Clock 33 7 Connect to Apollo Pro133A (1), South Bridge (1), and PCI slots (5)

USB Clock 48 1 Connect to South Bridge (1)

Super I/O Clock 24 1 Connect to Super I/O (1) if an external Super I/O is used

IOAPIC Clock 14.31818 1 Connect to Slot-1 or Socket-370 CPU

Reference Clock 14.31818 2 Connect to South Bridge (1) and ISA slots (1)

Note: The voltage level for CPU and IOAPIC clock signals is 2.5V. The voltage level for the remaining clocks is 3.3V.

Figure 2-21 shows clock connections of the system clock synthesizers to their respective destinations.

Super I/O

(If used)

System

Clock

Synthesizer

Reference CLK

PCICLK(1)

USBCLK

SDCLK[16:0]

Reference CLK

Super I/O CLK

Slot-1 or

Socket-370

CPU

IOAPIC CLK

CPUCLK

PCLK (5)

CPUCLK(1)

SDCLK

DCLKO

PCICLK(1)

VT82C694XVT82C686A

DIMM

Figure 2-21. System Clock Connections