Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 16 Motherboard Design Guidelines
Technologies, Inc.
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2.2.3.2 Six-Layer Board
Figure 2-8 illustrates an example of a six-layer stack-up with 4 signal layers and 2 power planes. The layer sequence of
component-ground-internal1-internal2-power-solder is the most common stack-up arrangement from top to bottom. It is
recommended to place a 5~6 mil substrate between the signal layer and the power plane and place 30~35 mil substrate between
two internal layers. A 7-mil substrate must be placed between the power plane and the internal layer. Dielectric constant, E
r
,
should be 4.5 for all substrate materials.
In order to reduce crosstalk effects between layers, signal traces on the two internal layers should be orthogonal. Routing any
signal trace on the power planes, either on the power layer or on the ground layer, is also not recommended on a six-layer board.
As an exception, if a signal has been routed on the power layer, then it should be routed as short as possible. In any case, routing
on the ground layer is not allowed. The impedance of all signal layers is to be in the range between 55 ohms and 75 ohms. Lower
trace impedance providing better signal quality is preferred over higher trace impedance for clock signals.
5~6 mils
7 mils
5~6 mils
Component layer (0.5 oz. Copper)
Ground layer (1 oz. Copper)
Solder layer (0.5 oz. Copper)
Power layer (1 oz. Copper)
30~35 mils
7 mils
Internal layer #2 (1 oz. Copper)
Internal layer #1 (1 oz. Copper)
Figure 2-8. Six-Layer Stack-up with 4 Signal Layers and 2 Power Planes