Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Preliminary Revision 0.5, November 19, 1999 Signal Connectivity and Design Checklist
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SDRAM Clock Trace Length Calculation
Pre-route SDRAM clock traces (SDCLK0~SDCLK15) from the system clock synthesizer to the DIMM slots as short as possible.
The length of all SDRAM clocks will be based on the longest one (L
SD
). The length of DCLKWR (L
DIN
) should be the same as
that of the SDCLKs. The DCLKO clock trace should be as short as possible. A calculation example is shown below.
Clock Trace Shortest
Length
Desired
Length
Allowable
Difference
Allowable
Range
Clock chip à SDCLK[15:0] L
SD
L
SD
0.5" 1"~4"
DCLKWR (Clock chip à NB) L
DIN
(assume < L
SD
+3")
L
SD
+ 4.5"
0.5" 5.5"~8.5"
DCLKO (NB à Clock chip) L
DOUT
L
DOUT
- 1"~9"
Note: Here, the 4.5" represents the estimated trace length added into DCLKI for SDRAM clock alignment.
AGP Clock Trace Length Calculation
Pre-route AGP clock traces from the pin GCLKO of the VT82C694X to the AGP slot as short as possible. Then the trace length
for the signal GCLK should be the GCLKO trace length plus 3 inches.
Clock Trace Shortest
Length
Desired
Length
Allowable
Difference
Allowable
Range
GCLKOUT (NB à AGP Slot) L
GOUT
L
GOUT
- 1"~9"
GCLKIN (NB à NB) L
GIN
L
GOUT
+ 3"
0.5" 4"~12"
Note: Here, the 3" represents the estimated trace length added into GCLKI for AGP clock alignment.
PCI Clock Trace Length Calculation
Pre-route PCI clock traces from the system clock synthesizer to the VT82C694X (NPCLK) and VT82C686A (SPCLK) as short as
possible. Then pre-route PCI clock traces PCLK0~PCLK4 from the system clock synthesizer to all PCI slots as short as possible.
The length of these clocks will be based on the longest one (L
5
). A calculation example is shown below.
Clock Trace Shortest
Length
Desired
Length
Allowable
Difference
Allowable
Range
Clock chip à VT82C694X (NB) L
NB
L
5
+ 3"
1" 4"~15"
Clock chip à VT82C686A (SB) L
SB
L
5
+ 3"
1" 4"~15"
Clock chip à PCI1 L
1
L
5
1" 1"~12"
Clock chip à PCI2 L
2
L
5
1" 1"~12"
Clock chip à PCI3 L
3
L
5
1" 1"~12"
Clock chip à PCI4 L
4
L
5
1" 1"~12"
Clock chip à PCI5 L
5
( > the others)
L
5
- 1"~12"
Note: Here, the 3" represents the estimated trace length added into NPCLK and SPCLK for PCI clock alignment.
Notes for the length calculation of all clock traces:
1. Shortest length means the minimum routable trace length between both clock ends. Desired length means the real length of the
clock traces on PCB layout. Allowable difference means the maximum difference between clock traces of the same type.
Allowable range means the acceptable clock length range for the specific clock.
2. The location of the system clock chip can affect the length of all clock traces. To optimize the clock alignment, place the clock
chip at an appropriate location.
3. In addition, the trace impedance of all clock traces should be in the range between 40 ohms and 55 ohms.