Product specifications

Design Guide - VT82C694X Apollo Pro133 with VT82C686A

Preliminary Revision 0.5, November 19, 1999 Signal Connectivity and Design Checklist

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5.4.3 Decoupling Recommendations Checklist

The high frequency and bulk decoupling capacitor distributions for major components are described in this section. Here, the high

frequency decoupling capacitors include 0.1uF (0603), 1uF (0805) and 4.7uF (1206) SMD ceramic capacitors. The bulk

decoupling capacitors include 10uF, 100uF and 1000uF electrolytic capacitors. The amount of bulk capacitors listed below is used

as reference. More capacitor distributions are recommended. These decoupling capacitors should be located as close to the

associated power and ground pins as possible.

For Slot-1 CPU, the decoupling capacitor requirements are listed below:

• VCC_CORE: 0.1uF x 9, 1uF x 10 and 1000uF x 6

• VTT: 0.1uF x 1, 1uF x1 and 100uF x 1

• VCC3: 0.1uF x 2, 1uF x 2 and 1000uF x 2

• VCC5: 0.1uF x 1, 1uF x 1

For Socket-370 CPU, the decoupling capacitor requirements are listed below:

• VCC_CORE: 0.1uF x 21, 1uF x 23, 4.7uF x 10 and 1000uF x 6

• VCC15: 0.1uF x 1, 1uF x1 and 1000uF x 4

• VREF: 0.1uF x 6, 1uF x 2 and 10uF x 1

• VCC25: 0.1uF x 1, 1uF x 1

• VCCCOMS: 0.1uF x 1, 1uF x 1

For Chipsets, the decoupling capacitor requirements are listed below:

• VT82C694X: 0.1uF x 8 or 1uF x 8

• VT82C686A: 0.1uF x 8 or 1uF x 8

For DIMM modules, the decoupling capacitor requirements are listed below:

• Two DIMM modules: 0.1uF x 9, 1uF x 10 and 1000uF x 2

• Three DIMM modules: 0.1uF x 12, 1uF x 15 and 1000uF x 4

• Four DIMM modules: 0.1uF x 16, 1uF x 20 and 1000uF x 5

For AGP slot, the decoupling capacitor requirements are listed below:

• +12V: 0.1uF x 1, 1uF x 1 and 10uF x 1

• VCC5: 0.1uF x 2, 1uF x 2 and 10uF x 1

• VCC3: 0.1uF x 9, 1uF x 9 and 1000uF x 1

• VDDQ (1.5V or 3.3V): 0.1uF x 11, 1uF x 11 and 1000uF x 2

Note: The capacitor of adjusting the SDRAM clock skew should be placed very near the ball AD25 (DCLKWR) of VT82C694X.

Its capacitance is dependent on the SDRAM clock layout.