Design Guide VT82C694X Apollo Pro133A with VT82C686A South Bridge Preliminary Revision 0.5 November 19, 1999 VIA TECHNOLOGIES, INC.
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect REVISION HISTORY Document Release 0.5 Date Revision Initials 11/19/99 Initial Release (Modified from DG694X&596BR070 and DG693A&686AR060) VL, JY, VH, RC, SS Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect TABLE OF CONTENTS Revision History ............................................................................................................................................i Table of Contents ..........................................................................................................................................i List of Figures ..........................................................................
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 2.3.2.6 AGP Clock Signals............................................................................................................................................. 36 2.3.2.7 PCI Clock Signals .............................................................................................................................................. 37 2.3.2.8 Miscellaneous Clock Signals ...............................................
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 5.4.6 Signal Trace Attribute Checklist................................................................................................................................ 94 Appendices ................................................................................................................................................. 95 Appendix A - SPKR Strapping Application Circuits..............................................
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A LIST OF FIGURES Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge ............................................................ 4 Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View) ............................................................ 7 Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View).......................
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A Figure 2-54. AC'97 Link Example.............................................................................................................................................. 62 Figure 2-55. MIDI/Game Port Application Circuit .................................................................................................................... 62 Figure 2-56. Hardware Monitoring Application Circuit............................
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A LIST OF TABLES Table 2-1. Different Board Size Lists for Slot-1 System ................................................................................................................ 9 Table 2-2. Different Board Size Lists for Socket-370 System....................................................................................................... 12 Table 2-3.
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Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A INTRODUCTION This document provides design guidelines for motherboard manufacturers on developing single Slot-1 or Socket-370 processor and Apollo Pro133A (VT82C694X) based systems. All the major underlying subsystems, especially Host Interface and Memory subsystems, related to the motherboard design are described in detail. General layouts, routing guidelines and power requirements of each subsystem are presented. 1.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 1.2 Apollo Pro133A Chipset Overview The Apollo Pro133A chip set consists of the VT82C694X system controller (510-pin BGA) and the VT82C686A PCI to ISA bridge (352-pin BGA). The features for both chips are listed below and a typical system block diagram is shown in this section. 1.2.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 1.2.2 Super South (VT82C686A) Chipset Features The VT82C686A Super-IO PCI Integrated Peripheral Controller (PSIPC) is a high integration, high performance, power efficient and high compatibility device that supports Intel and non-Intel based processors plus PCI bus bridge functionality to make a complete Microsoft PC98-compliant PCI/ISA system.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 1.2.3 System Block Diagram A block diagram of a typical Apollo Pro133A based system with a VT82C686A South Bridge is shown in Figure 1-1. The Apollo Pro133A supports a single processor including 64-bit Slot-1 (Intel Pentium II TM) or Socket-370 (Intel Celeron TM) CPUs at 66 MHz, 100 MHz or the maximum 133MHz system bus frequency.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 1.3 System Design Recommendations The VT82C694X Apollo Pro133A north bridge and VT82C686A south bridge form one of VIA's most optimized chipset combinations for single Slot-1or Socket-370 based PC systems.
Technologies, Inc. We Connect Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect MOTHERBOARD DESIGN GUIDELINES This chapter describes general design schemes and recommended layout rules. It begins with the 510-pin BGA (Pro133A north bridge) and 352-pin BGA (south bridge) ballout assignments. The following section contains the placement and routing of a motherboard, PCB stack-up information and power requirements for a desktop system.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.1.2 "Super South" South Bridge Ballout Assignment Ballout of the VIA "Super South" South Bridge is designed to minimize the number of crossover signals. Similarly to Figure 2-1, the major signal group quadrants are shown in Figure 2-2.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2 Motherboard Description This section illustrates proposed component placements for an Apollo Pro133A based motherboard with different system configurations to achieve maximum optimization. The description of the Printed Circuit Board (PCB) for a motherboard is also given. 2.2.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.1.1 ATX Form Factor for Slot-1 System A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in Figure 2-3. The major components on the board are single Slot-1 CPU, five PCI slots, one AMR, one ISA slot and three DIMM slots. This figure shows an ATX motherboard placement as a reference only.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.1.2 Micro ATX Form Factor for Slot-1 System A proposed component placement and signal group routings for an Apollo Pro133A micro-ATX system design is illustrated in Figure 2-4. The major components on the board are single Slot-1 CPU, two PCI slots, one AMR, one ISA slot and two DIMM slots. This figure shows a reference only micro-ATX motherboard placement.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.2 Socket-370 Motherboard Placement and Routing For Socket-370 CPU and Apollo Pro133A PC motherboard designs, two proposed placements and group signal routings for the two most popular form factors (ATX and micro-ATX) are shown in figures 2-5 and 2-6 respectively. Detailed layout guidelines and signal routings for the Pro133A chipset will be addressed later in section 2.4.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.2.1 ATX Form Factor for Socket-370 System A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in Figure 2-5. The major components on the board are single Socket-370 CPU, five PCI slots, one AMR, one ISA slot and three DIMM slots. This figure shows an ATX motherboard placement as a reference only.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.2.2 Micro ATX Form Factor for Socket-370 System A proposed component placement and signal group routing for an Apollo Pro133A micro-ATX system design is illustrated in Figure 2-6. The major components on the board are single Socket-370 CPU, two PCI slots, one AMR, one ISA slot and two DIMM slots. This figure shows a reference only micro-ATX motherboard placement.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.3 Printed Circuit Board Description A brief description of the Printed Circuit Board (PCB) for an Apollo Pro133A based system is provided in this section. From a cost-effectiveness point of view, a four-layer board is recommended for the motherboard design. For better quality, a six-layer board is preferred. These two types of boards will be discussed below: 2.2.3.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.3.2 Six-Layer Board Figure 2-8 illustrates an example of a six-layer stack-up with 4 signal layers and 2 power planes. The layer sequence of component-ground-internal1-internal2-power-solder is the most common stack-up arrangement from top to bottom. It is recommended to place a 5~6 mil substrate between the signal layer and the power plane and place 30~35 mil substrate between two internal layers.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.4 On Board Power Regulation Currently, the voltage range of the Slot-1 processor core voltage (VCC_CORE) is between 2.1V and 3.3V. And the voltage range of the Socket-370 processor core voltage is between 1.3V to 2.05V. Local regulation of VCC_CORE is recommended.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.5.1 Single Slot-1 Processor Capacitive Decoupling Figure 2-10 shows a suggested decoupling capacitor placement for the Slot-1 CPU. The isolation region between any two of the VCC_CORE (Core voltage 2.1V~3.3V) island, the VCC3 (I/O voltage 3.3V) island, the VTT (GTL+ termination voltage 1.5V) island and the VCC5 (5V) should be at least 30 mil wide.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.5.2 Single Socket-370 Processor Capacitive Decoupling A suggested decoupling capacitor placement for the Socket-370 CPU is shown in Figure 2-11. The high frequency decoupling capacitors (0.1uF and 1uF) should be located as close to the power and ground pins of the Socket-370 as possible.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.5.3 Apollo Pro133A Chipset Capacitive Decoupling Decoupling capacitors for the VT82C694X and VT82C686A are shown in Figure 2-12. It is recommended to place decoupling capacitors as close to the chips as possible and evenly distribute these capacitors around them. In most cases, the value of these decoupling capacitors is 1uF, but 0.1uF capacitors are also acceptable.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.6 Power Plane Partitions The required voltage sources in an Apollo Pro133A system design are: +/-12V, +/-5V, CPU core voltage (1.3V~3.3V defined by the five voltage identification pins of the Slot-1 or Socket-370 CPU), 3.3V, 2.5V and 1.5V. The power layer is partitioned into several power islands with five major power sources: VCC_CORE (CPU core voltage), VCC3 (3.3V), VTT (1.5V GTL+ termination voltage), VDDQ (3.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Back Panel Area VCC5 Island VCC5 Island VCC_CORE Island VCC3 Island VTT Island 694X VDDQ Island 510-PIN CLK GEN. VCC3 Island VT82C 686A IDE1 IDE2 VCC5 Island FDC VCC5 Island Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.6.2 Power Plane Partitions for Socket-370 Motherboard Figure 2-16 shows the power plane partitions on a typical ATX form factor. The island associated with VCC_CORE covers the whole area of the PPGA socket for the Socket-370 CPU. The VCC3 island covers an area that contains the North Bridge chip, the South Bridge chip, all DIMM slots and a half of the AGP slot. The VDDQ island occupies most AGP signal routing area.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Back Panel Area VCC_CORE Island VCC5 Island 37 Socket 370 VCC5 Island 1 A AN VCC3 Island 694X VDDQ Island CLK GEN. 510-PIN VCC3 Island VT82C 686A IDE1 IDE2 VCC5 Island FDC VCC5 Island Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.7 Chipset Power and Ground Layout Recommendations This section shows the recommended layout of the power plane and the ground plane on each layer for the two VIA BGA chips (VT82C694X and VT82C686A). Appropriate power and ground distributions for component, ground, power and solder layers can provide a better power and ground circuit to the chip.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect (a) Component Layer (b) Ground Layer (c) Power Layer (d) Solder Layer Figure 2-19. VT82C686A Power and Ground Layout Notes: 1. In Figure 2-19 (b) and (c), a black round dot represents a via with no connection to the specified layer and a white round dot represents a via with a connection to the specified layer.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.8 Power Up Configuration During system restart and power up, system configuration information is latched at the rising edge of the RESET# signal. All signals used to select power-up strap options are connected to either internal pull-up or pull-down resistors of minimum 50K ohms (maximum is 150K ohm). These internal resistors select a default mode on the signal during reset.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.2.8.1 VT82C694X Power Up Strappings Internal configuration registers of Apollo Pro133A digital core logic are based on the status of memory address lines (MAB[12:11]#, MAB10, MAB[9:6]#) and Host address lines (A15# and A7#). These memory address signals are pulled up or pulled down with internal resistors on their I/O buffers to determine the default configurations.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3 General Layout and Routing Guidelines This section provides general layout rules and routing guidelines for designing Apollo Pro133A motherboards. 2.3.1 Trace Attribute Recommendations For most signal traces on an Apollo Pro133A motherboard layout, 5-mil trace width and 10-mil spacing are advised. To reduce trace inductance, minimum power trace width is set at 30 mils.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2 Apollo Pro133A Clock Layout Recommendations 2.3.2.1 Clock Requirements The requirements of the system clock synthesizer for an Apollo Pro133A based system design are listed in Table 2-7. Table 2-7.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.2 Clocking Scheme The 17 (66 / 100 / 133MHz) SDRAM clocks are generated from a clock buffer inside the system clock synthesizer. They are controlled by the SDRAM clock output (DCLKO) provided by the Apollo Pro133A North Bridge. The VT82C694X (North Bridge) has a built-in de-skew Phase Lock Loop (PLL) circuitry for optimal skew control within and between clocking regions. For more details, refer to Figure 2-22.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.3 Clock Routing Considerations Clock routing guidelines are listed below: • • • • • • The recommended range of a clock trace width is between 15 mils and 20 mils. The minimum space between one clock trace and adjacent clock traces is 15 mils. The minimum space from one segment of a clock trace to other segments of the same clock trace is two times of the clock width.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.4 System Clock Combinations The major clock combinations for an Apollo Pro133A based system are listed in Table 8. Clock frequencies for the AGP clock and PCI clock are 66MHz and 33MHz respectively. Various clock combinations for the CPU clock and the SDRAM clock are determined by power-up strap options on MAB12# and MAB8#. Table 2-8.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.5 Host CPU Clock and SDRAM Clock Signals Layout recommendations for host clocks and SDRAM clocks for Slot-1 and Socket-370 CPUs are shown in Figure 2-26 and 2-27 respectively. 22 ohm and 10 ohm series terminations are recommended for all host clocks and all SDRAM clocks respectively. It is also recommended that bypass capacitors be added to all clock signals on the clock synthesizer side.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 0 ~ 33 ohm 10 ~ 33 pF Socket-370 CPU LNB CPUCLK VT82C694X LNB HCLK HCLK LDOUT 0 ~ 33 ohm DCLKO SDCLKIN (as short as possible) LSD + 4.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.6 AGP Clock Signals Layout recommendations for the AGP clock are shown in Figure 2-28. Typically, 22 ohm series terminations are recommended for the AGP clock. A typical 22 pF bypass capacitor is also required for the AGP clock (GCLKO) to the AGP slot. Depending on how the system is designed, the value of the bypass capacitors for the PCI clocks may vary.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.7 PCI Clock Signals Layout recommendations for the PCI clocks are shown in Figure 2-29. Typically, 22 ohm series terminations are recommended for all PCI clocks. A typical 22 pF bypass capacitor is also required for each PCI clock. Depending on how the system is designed, the value of the bypass capacitors for the PCI clocks may vary.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.2.9 Clock Trace Length Calculation The calculation is based on the recommended placements shown in sections 2.2.1 and 2.2.2. A different component placement may result in a different calculation for the clock trace length.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A AGP Clock Trace Length Calculation Pre-route AGP clock traces from the pin GCLKO of the VT82C694X to the AGP slot as short as possible. Then the trace length for the signal GCLK should be the GCLKO trace length plus 3 inches. Clock Trace GCLKOUT (NB à AGP Slot) GCLKIN (NB à NB) Shortest Length LGOUT LGIN Desired Length LGOUT LGOUT + 3" Allowable Difference 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.3.3 Routing Styles and Topology High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state. In order to maintain better signal quality, transmission stubs should be kept under 1.5 inches. Therefore, daisy chain style routing is strongly recommended for these signals.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines 2.4.1 Host CPU Interface Layout and Routing Guidelines The GTL+ signals (host address bus, host data bus and host control signals) are typical point-to-point connections between CPU and North Bridge in a Slot-1 or Socket-370 system design. VTT (1.5V) terminations are required for GTL+ signals.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.1.2 Socket-370 Host Interface to North Bridge The recommended topology for the Socket-370 host signals to North Bridge (VT82C694X) is shown in Figure 2-34. For signal quality considerations, the trace length of the host signals should be minimized. 56 ohm pull-ups to VTT near the Socket-370 CPU are required. • • • It is recommended to route all host signals to VT82C694X in equal length and as short as possible.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A (a) Component Side (b) Solder Side Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.1.3 CPU Host Interface to South Bridge The host control signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed in Table 2-9. Except for FERR#, all signals are open drain (OD). 2.5V pull-ups are required for those open drain signals on the VT82C686A chip side. Table 2-9.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect A layout example for the remaining control signals between the VT82C686A chip and the Slot-1 CPU is shown in Figure 2-37. VCC2_5 330 ohm VT82C686A Slot-1 CPU (South Bridge) INIT SLP# SMI# STOPCLK# INIT SLP# SMI# STOPCLK# FERR# FERR# CPURST Layout these traces as short as possible No Connect Figure 2-37.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.2 Memory Subsystem Layout and Routing Guidelines 2.4.2.1 DRAM Routing Guidelines Most DRAM signals are multi-drop connections. A brief description of the memory subsystem signals is provided in Table 2-10 below. Table 2-10.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect VT82C694X DIMM4 (North Bridge) 2" < L1 < 2.5" DIMM3 0.4" < L2 < 0.5" DIMM2 DIMM1 0.4" < L4 < 0.5" 0.4" < L3 < 0.5" MD[63:0] MECC[7:0] CASA[7,6,4:2,0]# 2" < L5 < 3" MAA[14:0] SWEA# SRASA# SCASA# CASA[5,1]# 2" < L6 < 3.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect VT82C694X DIMM3 (North Bridge) 2" < L1 < 3" DIMM2 0.4" < L2 < 0.5" DIMM1 0.4" < L3 < 0.5" MD[63:0] MECC[7:0] CASA[7,6,4:2,0]# 2" < L4 < 3.5" MAA[14:0] SWEA# SRASA# SCASA# CASA[5,1]# 2" < L5 < 4" MAB[14:0]# SWEB# SRASB# SCASB# CASB[5,1]# RASA[1:0]# RASB[1:0]# RASA[3:2]# RASB[3:2]# RASA[5:4]# RASB[5:4]# RASA[7:6]# RASB[7:6]# No Connet (Group B) (Group A) Note: MAB[14:0]# represents MAB[14:11]#, MAB10 and MAB[9:0]#.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect DIMM3 VT82C694X DIMM2 DIMM1 (North Bridge) 0.4" < L2 < 0.5" 0.4" < L3 < 0.5" 2" < L1 < 3.5" MD[63:0] MECC[7:0] CASA[7,6,4:2,0]# 2" < L4 < 3.5" 0.4" < L5 < 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect VT82C694X DIMM2 (North Bridge) 2" < L1 < 3.5" DIMM1 0.4" < L2 < 0.5" MD[63:0] MECC[7:0] CASA[7:0]# MAA[14:0] SWEA# SRASA# SCASA# RASA[1:0]# RASB[1:0]# 2" < L3 < 4" RASA[3:2]# RASB[3:2]# (Group A) MAB[14:0]# No Connet SWEB# SRASB# SCASB# No Connet CASB[5,1]# No Connet RASA[5:4]# RASB[5:4]# No Connet RASA[7:6]# RASB[7:6]# No Connet Note: MAB[14:0]# represents MAB[14:11]#, MAB10 and MAB[9:0]#. Figure 2-42.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect The reference layout for three-DRAM DIMM slots is shown in Figure 2-44 below. In this layout example, no DRAM trace is over 4 inches long and those traces are also evenly distributed. (a) Component Side (b) Solder Side Figure 2-44. Layout Example of Three-DRAM DIMM Slots Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.3 AGP (4X Mode) Interface Layout and Routing Guidelines This section describes layout and routing guidelines to insure a robust AGP 4X mode interface design. The following guidelines will help insure that the AGP specification can be met. The system designer should do appropriate analysis and simulation to verify that the design fulfills AGP specification requirements. 2.4.3.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.3.2 Vref Characteristics for AGP 4X Mode Vref is a DC voltage reference signal used to set the input sense level on the AGP bus. Vref is set at 0.5 x VDDQ (between 0.48 x VDDQ and 0.52 x VDDQ) for AGP 4X mode. Referring to Figure 2-46 for an AGP 4X mode implementation, two unidirectional Vref pins are provided in the connector. These pins connect Vref between the add-in card graphics chip and the VT82C694X chip.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Figure 2-47 shows an application example for the VDDQ Voltage-Switching circuit shown in Figure 2-46. Signal TYPEDET# is used to determine the VDDQ voltage level (1.5V or 3.3V) for the AGP interface. When TYPEDET# is high, Q1 is always turned on. The VDDQ output voltage is provided directly by the VCC3 (3.3V). When TYPEDET# is low, the VDDQ output voltage is 1.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.3.4 AGP VDDQ Power Plane Partition By referring to the power plane partition examples in figures 2-15 to 2-16, the power plane for the AGP slot should be separated from the remaining power planes on the motherboard. A VDDQ Island (selected area) will cover most of the AGP signal routing area. The detailed VDDQ power plane partition is shown in Figure 2-49. Figure 2-49.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 2.4.3.5 Optimized Layout and Routing Recommendations It is strongly recommended to maintain the trace length of all AGP (especially Data and Strobe) signals less than 4 inches. It is always best to reduce line mismatch to add to the timing margin. In other words, a balanced topology can match trace lengths within the groups to minimize skew.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect (b) Solder Side Figure 2-50. AGP 4X Interface Layout Example Notes: 1. Most Decoupling capacitors are placed on the left-hand side of the AGP slot in Figure 2-50 (a). 2. Discrete pull-up resistors are located very near their associated pins for the short stub limitation in Figure 2-50 (a). 3. Each Strobe signal is centered within its group to minimize the signal to strobe skew. 4.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.4.4 PCI Interface Layout and Routing Guidelines It is recommended that the VT82C694X and VT82C686A be placed at both ends of the PCI bus for better signal termination. A topology example of the AGP and PCI buses on an ATX form factor is shown in Figure 2-51 below. PCI signal traces may be placed on either the component layer or the solder layer. Most AGP signal traces should be placed on the component layer.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5 Super South (VT82C686A) Layout and Routing Guidelines 2.5.1 USB controller The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial interface for adding external peripheral devices such as game controllers, communication devices, and input devices on a single bus. Brief descriptions of the USB signals of the VT82C686A are listed in Table 2-12.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect The layout guidelines for USB are listed below. • • Each pair of USB data signals is required to be parallel to each other with the same trace length. Each pair of USB data signals is required to be parallel to a respective ground plane. A routing example of two pairs of USB data buses is shown in figure 2-53 below.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5.2 AC’97 Link and Game/MIDI Ports Table 2-13 shows a brief description of the signals of AC'97 Link Controller and Game Ports. All those signals are multi-function pins with the second IDE channel bus. To enable both functions, the power up strapping of SPKR (pin V5 of the VT82C686A) must be pulled up to VCC3 with a 4.7K~10K ohm resistor. Table 2-13.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect VT1611A VT82C686A (Audio Codec) (South Bridge) 22 ohm BITCLK SDIN SDIN2 BITCLK SDATA_IN 10K ohm 10K ohm 22 ohm ACRST# SYNC SDOUT RESET# SYNC SDATA_OUT AC'97 Codec AC'97 CONTROLLER Figure 2-54. AC'97 Link Example 2.5.2.2 Game/MIDI ports The VT82C686A supports two direct game ports (Joystick A and Joystick B) and one MIDI port interface. An application circuit of MIDI/Game port is shown in Figure 2-55.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5.3 Hardware Monitoring The hardware monitoring interface includes five positive voltage sensing inputs (four external and one internal), three temperature sensing inputs (two external and one internal), two fan-speed monitoring inputs and one chassis intrusion detection input. Programmable control, status, monitor and alarm are supported by the VT82C686A for flexible desktop management.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A Voltage Monitoring Typically VCC2 (core voltage of the CPU), VCCI (2.5V, core voltage of the VT82C694X), VCC3 (3.3V), 5V, and +12V are the five monitored voltage inputs. VCC2 and VCCI can be directly connected to the inputs. The +5V and 12V inputs should be attenuated with external resistors to any desired value within the input range.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5.5 System Management Bus Interface The I2C bus signal pair of the VT82C686A will handle all I2C buses to other on-board devices such as the Clock Synthesizer and the three DIMM slots. A block diagram of System Management Bus Interfaces is shown in Figure 2-57. It is recommended to place both pull-ups at the end of the I2C bus.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5.6 IDE Both Primary and secondary IDE channels have their own control signals. The Primary IDE channel has a dedicated data bus. However, the secondary IDE data bus is multiplexed with an Audio/Game port or it can share ISA address bus SA[15:0] as SDD[15:0]. The two options are listed below for selecting the secondary IDE data bus.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Dual channel master mode PCI supports four Enhanced IDE devices. The transfer rate for each device can support up 33 MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface. Transmission line effects and signal crosstalk emerge in the IDE related signals. To eliminate ringing and reflection caused by the transmission line effect, trace length and impedance match must be taken into account.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Ultra DMA/66 Interface Layout Guidelines VT82C686A supports Ultra DMA/66 IDE interfaces on both Primary IDE channel (IDE1) and Secondary IDE channel (IDE2). A Micro-ATX component placement example for implementing the Ultra DMA/66 interface (option 2) is shown in Figure 2-60. The detailed placement for the VT82C686A chip and two IDE connectors is illustrated in the lower left corner of the figure.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect The application circuit of the ultra DMA/66 IDE interface is shown in Figure 2-61. The 80-conductor cable, required by the ultra DMA/66 IDE interface, is the major difference from the 40-conductor cable of the current IDE interface. For the detection of the 80-conductor cable, pin 34 (CBLID) of IDE connector may be used to provide a signal state from an ultra DMA/66 device to a GPI pin of the South Bridge Controller.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5.7 Suspend to DRM Power-on-suspend (POS), Suspend-to-RAM (STR) and Suspend-to-Disk (STD) or so called Soft-off are three different suspend states supported by the VT82C686A. These suspend functions are implemented not only in a notebook PC design but also in a desktop PC design. And the STR function is specially described in this section. 2.5.7.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 2.5.7.2 STR Power Plane Control VT82C686A controls the system entering the various suspend states through the suspend control signals listed in Table 2-14.
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect TIMING ANALYSIS AND SIMULATION The 133 MHz timing analysis here will provide a basis for the concept of trace length limitation for some high speed buses and control signals such as the CPU address bus (A[31:3]). A brief analysis is given for each diagram. 133 MHz system frequency is assumed where one clock (1T) represents 7.5 ns. Reasons for the limited lengths of some signals (referring to Section 2.
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect ELECTRICAL SPECIFICATIONS This section describes the electrical specifications of the VT82C694X. 4.1 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation is not implied under the ratings listed in Table 4-1. Table 4-1.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 4.3 DC Characteristics DC characteristics of the VT82C694X are shown in Table 4-3. Table 4-3. DC Characteristics Symbol VIL VIH VOL VOH IIL IOZ ICC1_5 ICC3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Tristate Leakage Current Power Supply Current (GTL) Power Supply Current Min -0.5 +2.0 2.4 - Max +0.8 VCC+0.5 0.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A SIGNAL CONNECTIVITY AND DESIGN CHECKLIST 5.1 Overview The Apollo Pro133A North Bridge, and VT82C686A South Bridge are the two major components in a VIA Apollo Pro133A based PC system. Two signal connectivity tables for both North Bridge and South Bridge and a design checklist are given in the following sections. Pin connections may vary in different circuit designs.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 5.2 VT82C694X Apollo Pro133A North Bridge The connectivity for each signal of the VT82C694X North Bridge is listed in Table 5-1. Motherboard designers can use this table as a quick reference to review their schematics. Table 5-1.
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Signal Name HCLK DCLKO DCLKWR GCLKO GCLK PCLK RESET# PWROK GCKRUN# / GPAR SUSCLK SUSTAT# CPURSTI# CLKRUN# I/O I O I O I I I I O/IO I I I I CLOCK AND RESET CONTROL Connection Connect to the CPU clock output of the system clock synthesizer. Connect to the SDRAM clock input of the system clock synthesizer. Connect to the SDRAM clock output of the system clock synthesizer.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 5.3 "Super South" South Bridge Controller The connectivity for each signal of VT82C686A South Bridge is listed in Table 5-2. Motherboard designers can use this table as a quick reference to review their schematics. Some pins have been repeatedly described for different functions in different subtables, please be careful in using the following table. Table 5-2.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Signal Name SA[19:16] SA[15:0]/SDD[15:0] LA[23:20] SD[15:0] SBHE# IOR# IOW# MEMR# MEMW# SMEMR# SMEMW BALE IOCS16# MCS16# IOCHCK#/GPI0 IOCHRDY RFSH# AEN IRQ1/MSCK IRQ[5:3] IRQ6/ GPI4/ SLPBTN# IRQ7 IRQ8#/GPI1 IRQ[11:9] IRQ12/MSDT IRQ[15:14] DRQ[1:0] DRQ2/ SERIRQ/ GPIOE/ OC1# DRQ3 DRQ[7:5] DACK[1:0]# DACK2#/ GPIOF/ OC0# DACK3# DACK[7:5]# TC SPKR ISA BUS INTERFACE I/O Connection IO Connect to ISA slots and BIOS ROM. 4.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect USBCLK USB INTERFACE I/O Connection IO Connect to USB(0) connector. 47pF capacitor to ground with 27 ohm resistor, and then 15K ohm resistor to ground. These passive components should be placed as close to VT82C686A as possible I Connect to the corresponding USB(0) over-current detection voltage divider. I IO IO Connect to USB(1) connector.
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect AUTOFD# PINIT# SLCTIN# STROBE# ACK# BUSY ERROR# PE SLCT PARALLEL PORT INTERFACE I/O Connection IO Connect to the printer connector. 4.7K ohm pull-up to VCC and a 180pF decoupling capacitor to ground. These passive components should be placed near the connector. IO Same as the above. IO Same as the above. IO Same as the above. IO Same as the above. I Same as the above. I Same as the above. I Same as the above.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect RXD2 RTS2# CTS2# DTR2# DSR2# DCD2# RI2# IRTX/GPO14 IRRX/GPO15 SERIAL PORTS AND INFRARED INTERFACE I/O Connection O Connected to a corresponding 9-pin serial connector (usually COM1) through a serial RS232 interface buffer and a 330pF decoupling capacitor to ground. I Same as the above. O Same as the above. I Same as the above. O Same as the above. I Same as the above. I Same as the above. I Same as the above.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Signal Name GPI0/IOCHCK# GPI1/IRQ8# GPI2/BATLOW# GPI3/LID GPI4/IRQ6/ SLPBTN# GPI5/PME#/THRM GPI6/SMBALRT# GPI7/RING# GPI8/GPO8/GPIOA/G POWE# GPI9/GPO9/GPIOB/ FAN2 GPI10/GPO10/GPIOC/ CHAS GPI11/GPO11/ GPIOD I/O I I I I I GENERAL PURPOSE INPUTS Connection 4.7K ohm pull-up to VCC3 if no multiplexed function is applied. 10K ohm pull-up to 3VSB if its function is applied. Same, if not applied. 4.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Signal Name GPIOA(GPIO8) GPIOB(GPIO9)/FAN2 GPIOC(GPIO10)/ CHAS GPIOD(GPIO11) GPIOE/ OC1/ SERIRQ/ DRQ2 GPIOF/ OC0/ DACK2# GENERAL PURPOSE I/O I/O Connection IO 4.7K ohm pull-up to VCC3 if no multiplexed function is applied. IO Same as the above. IO Same as the above. IO IO I I I IO I I Same as the above. Same as the above. Same as the above.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect POWER MANAGEMENT Signal Name I/O Connection PME#/THRM/GPI5 10K ohm pull-up to 3VSB if the function is not applied. I PWRBTN# Connect to Power Button circuitry. I SLPBTN#/IRQ6/GPI4 10K ohm pull-up to VCC3 if the function is not applied. I RSMRST Connect to Resume Reset circuitry. I EXTSMI# IOD 10K ohm pull-up to 3VSB if the function is not applied. SMBALRT#/GPI6 10K ohm pull-up to 3VSB if the function is not applied.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 5.4 Apollo Pro-133A Design Checklist This Apollo Pro-133A (VT82C694X and VT82C686A) design checklist provides six checkup lists as a brief layout reference for implementing most layout requirements. 5.4.1 General Layout Considerations Checklist For most signal traces on an Apollo Pro133A motherboard layout, 5-mil trace width and 10-mil spacing are advised.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 5.4.3 Decoupling Recommendations Checklist The high frequency and bulk decoupling capacitor distributions for major components are described in this section. Here, the high frequency decoupling capacitors include 0.1uF (0603), 1uF (0805) and 4.7uF (1206) SMD ceramic capacitors. The bulk decoupling capacitors include 10uF, 100uF and 1000uF electrolytic capacitors.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A 5.4.4 Clock Trace Checklist The general clock routing guidelines are listed below: • • • • • • The recommended range of a clock trace width is between 15 mils and 20 mils. The minimum space between one clock trace and adjacent clock traces is 15 mils. The minimum space from one segment of a clock trace to other segments of the same clock trace is two times of the clock width.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect SDRAM Clock Trace Length Calculation Pre-route SDRAM clock traces (SDCLK0~SDCLK15) from the system clock synthesizer to the DIMM slots as short as possible. The length of all SDRAM clocks will be based on the longest one (LSD). The length of DCLKWR (LDIN) should be the same as that of the SDCLKs. The DCLKO clock trace should be as short as possible. A calculation example is shown below.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect 5.4.6 Signal Trace Attribute Checklist The maximum accumulated trace length as a brief layout reference for high-speed or critical signal groups (e.g. host and memory) is listed in Table 5-4. The accumulated trace length represents the total trace length or the length sum of two traces before and after a damping resistor. It is recommended to route the same signal groups in equal length and as short as possible.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A APPENDICES The following schematics are provides "as is" with no warranties whatsoever, including any warranty of merchantability, fitness of any particular purpose, or any warranty otherwise arising out of proposal, specification or sample. No license, express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. VIA Technologies, Inc.
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Appendix A - SPKR Strapping Application Circuits Power-up strapping for the VT82C686A SPKR pin (pin V5) determines the function of the Secondary IDE disk data bus pins (SDD[15..0]) to be either SDD[15..0] (SPKR strapped low) or Audio/Game port functions (SPKR strapped high).
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Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines B.1 Introduction This document describes the Printed Circuit Board (PCB) layout recommendations for VIA VT1611A (AC’97 audio codec) and Game/MIDI port in a motherboard design. The main focus is on how to improve the audio quality. Electromagnetic interference (EMI) issues are not considered in the document.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect B.2 Layout Recommendations In this section, the layout recommendations on component placement, ground and power plane partitions and routing guidelines are described in detail. The PCB layer sequence used here is Signal (Component)-Ground-Power-Signal (Solder). B.2.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect These high frequency decoupling capacitors should be routed on the component layer with wide traces to reduce impedance and placed on their respective ground plane. Low frequency decoupling capacitors (basically greater than or equal to 10uF, Electrolytic or Tantalum) are used to prevent power supply droop during load transient.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Table B-3. AC-Coupling Capacitors for Audio Input Signals Audio Output Signals LINE_OUT_L LINE_OUT_R MONO_OUT LNLVL_OUT_L LNLVL_OUT_R AC-Coupling Capacitors C17 C18 None None None Note 1 1 1,2 1,2 1,2 Notes 1. Use all ac-coupling capacitors in 1206 package. 2. Use the same ac-coupling mechanism when the function is applied. These audio input ac-coupling capacitors in Table B-2 should be placed near the audio codec.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect B.2.2 Ground and Power Planes: It is recommended to include partitioned digital and analog power planes directly over their respective ground planes. The powerground sandwich with a substrate separation can provide an extremely effective, low ESR & ESL bypass capacitance. The audio IC leads will have pads and vias that go directly to the appropriate plane for power and ground.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Table B-4. Signal Groups Associated with Their Audio Ground Plane Ground Planes GND_AUD GND_LOUT GND_MIDI Digital Ground Audio Signals Audio input signals: AUX_L. AUX_R, VIDEO_L, VIDEO_L, VIDEO_R, CD_L.
Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A B.2.3 Routing Guidelines Routing to VDD, VREF, AFILT and FILT capacitors All high frequency decoupling, reference high frequency decoupling and filter capacitors must be routed on the same layer as the codec. This is done to reduce inductance in the supply, reference and filter networks. Inductive loops in these networks can be a coupling mechanism for high frequency noise.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Figure B-5. Component Layer Layout Example Figure B-6. Solder Layer Layout Example Preliminary Revision 0.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Table B-5 and Table B-6 show the layout guideline summary for signal and power/ground nets respectively in the reference schematic. Table B-5.
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Technologies, Inc. We Connect Design Guide - VT82C694X Apollo Pro133 with VT82C686A Appendix C - Apollo Pro133A Reference Design Schematics Apollo Pro133A Reference design schematics are shown in the following 20 pages. The component placement for this reference design is shown in Figure C-1.
Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect Figure C-1. Apollo Pro133A Reference Component Placement Preliminary Revision 0.
1 2 3 4 VIA Preliminary Customer Reference Schematics MODEL:VT5228C A (SLOT 1+VT82C694A/X+VT82C686A+AGP2X/4X MODE+STR FUNCTION) VER:0.
1 2 3 4 SLOT1 PENTIUM-II -CPUINIT -CPURST INTR NMI -SMI -STPCLK -SLP R96 330 -CPUINIT -CPURST CPUCLK A75 AP0 AP1 AERR GTL BPRI BNR LOCK ADS DRDY DBSY TRDY HIT HITM DEFER RP RSP DEP0 DEP1 DEP2 DEP3 DEP4 DEP5 DEP6 DEP7 RS0 RS1 RS2 BPM0 BPM1 BP2 BP3 FERR IGNNE A20M PICD0 PICD1 PICCCLK GTL PWRGOOD 2.5V BCLK 2.5V GTL PREQ PRDY GTL BERR BINIT IERR FRCERR 2.5V GTL 2.5V INTR/LINT0 NMI/LINT1 SMI STPCLK SLP FLUSH INIT RESET VID0 VID1 VID2 VID3 VID4 VID0 VID1 VID2 VID3 VID4 2.
1 2 3 4 M21 M22 U6 W21 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCIRST PREQ0 PREQ1 PREQ2 PREQ3 PREQ4 PGNT0 PGNT1 PGNT2 PGNT3 PGNT4 C_BE0 C_BE1 C_BE2 C_BE3 R117 75 1% K6 K2 K4 K3 K5 J1 J2 H2 H1 J5 H3 H5 H4 G1 G2 G4 D1 D3 D2 C1 A2 C3 B3 D4 E5 A4 D5 B4 B5 A5 E6 C6 A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 A_D8 A_D9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_D16 A_D17 A_D18 A_D19 A_D20 A_D21 A_D22 A_D2
1 2 3 MD[32..63] 4 MD[32..
1 2 3 4 U20 A PD_A0 PD_A1 PD_A2 -PDCS_1 -PDCS_3 -DDACK_A DDREQ_A -DIOR_A -DIOW_A HDRDY_A A_D[0..31] B C_-BE[0..
1 2 SA[0..23] SD[0..
1 2 3 4 VCC2_5 A 1 3 5 7 A RN31 10K 8P4R 1 3 5 7 -A20M U11 2 4 6 8 JFREQ1 2 4 6 8 2 4 6 8 11 13 15 17 RATIO0 RATIO1 RATIO2 RATIO3 -A20M_ -IGNNE_ INTR_ NMI_ VCC3 1 19 R298 10K A0 A1 A2 A3 A4 A5 A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 18 16 14 12 9 7 5 3 -IGNNE INTR NMI VCC2_5 OE0 OE1 V 20 LV244A Fraction /Ratio 2 3 4 5 5/2 7/2 9/2 11/2 -CRESET 1 U18A 2 F04 B R299 1K JFREQ1 1-2,3-4,5-6,7-8 1-2,5-6,7-8 3-4,5-6,7-8 5-6,7-8 1-2,3-4,7-8 1-2,7-8 3-4,7-8 7-8 B R324 2K U21 SD0 SD1 SD2 SD3 BSEL0
1 2 3 4 MD[0..
1 2 3 4 MD[0..
1 2 3 4 PCI1 -12V VCC3 -INTR_C -INTR_A -INTR_C -INTR_A A PCICLK1 -REQ0 -REQ0 A_D31 A_D29 A_D31 A_D29 A_D27 A_D25 A_D27 A_D25 C_-BE3 A_D23 C_-BE3 A_D23 A_D21 A_D19 A_D21 A_D19 A_D17 C_-BE2 A_D17 C_-BE2 -IRDY -IRDY B -DEVSEL -DEVSEL -PLOCK -PERR -PLOCK -PERR -SERR -SERR C_-BE1 A_D14 C_-BE1 A_D14 A_D12 A_D10 A_D12 A_D10 A_D8 A_D7 A_D8 A_D7 A_D5 A_D3 A_D5 A_D3 A_D1 A_D1 -P1ACK64 -P1ACK64 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
1 2 3 4 VDDQ VCC3 -GDEVSEL R168 -GSTOP R180 8.2K -GSERR R186 8.2K -GPERR R181 8.2K USB_D0+ GPAR R185 8.2K -RBF R119 8.2K -INTR_B GCLKO -GREQ -PIPE R111 8.2K -WBF R120 8.2K -GREQ R109 8.2K R104 R124 8.2K AD_STB1 R144 8.2K AD_STB0 R192 8.2K -GFRAME R156 8.2K -GTRDY R167 8.2K R158 -GIRDY ST0 ST2 -RBF SBA0 8.2K SB_STB SBA2 SB_STB SBA4 SBA6 GD31 GD29 8.2K GD27 GD25 VDDQ C158 .1u C125 .1u AD_STB1 GD23 B C106 .1u C136 .1u C153 .
1 2 3 4 SL1 RES_DRV IRQ9 RES_DRV IRQ9 DREQ2 -5V -12V -0WS +12V A -SMEMW -SMEMR -IOW -IOR -DACK3 DREQ3 -DACK1 DREQ1 -REFRESH SYS_CLK IRQ7 IRQ5 IRQ4 IRQ3 TC BALE ISA_OSC B -MEMCS16 -IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 -DACK0 DREQ0 -DACK5 DREQ5 -DACK6 DREQ6 -DACK7 DREQ7 -SMEMW -SMEMR -IOW -IOR -DACK3 DREQ3 -DACK1 DREQ1 -REFRESH SYS_CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 -DACK2 TC BALE ISA_OSC -MEMCS16 -IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 -DACK0 DREQ0 -DACK5 DREQ5 -DACK6 DREQ6 -DACK7 DREQ7 -MASTER 32 33 3
1 2 R345 SIO_RES SIO_RES PW_LED 3 9 U18D 8 11 F04 U18E 10 300 A U18C 6 5 33 R325 4 RES_DRV F04 R323 A -IDERST 33 F04 PW_BN PW_BN PW-BT -EXTSMI -EXTSMI EXTSMI R333 100 SPEAK 22 R332 C 2 4 6 8 10 12 14 16 18 20 HD_LED1 R330 HD-LED 1K RST_SW R331 C173 .1uF BQ16 3904 SPEAK 2K E PANEL1 1 3 5 7 9 11 13 15 17 19 PW_LED PW-LED RESET IDE1 B PD_D[0..15] SD[0..
1 2 3 R141 4 10K DCLK6 DCLK5 DCLK7 DCLK8 C142 C144 C126 C128 10p 10p 10p 10p DCLK1 DCLK2 DCLK4 DCLK3 C143 C151 C139 C127 10p 10p 10p 10p DCLK11 DCLK12 DCLK9 DCLK10 C137 C138 C145 C149 10p 10p 10p 10p CPUCLK HCLK DCLKO C122 C123 C141 10p 10p 10p NPCLK SPCLK C124 C150 10p 10p PCICLK1 PCICLK2 C132 C131 10p 10p VCC3 L29 CK_VDD1 FB C117 .1u A C116 .1u C130 .1u VCC2_5 C140 .1u C129 .1u C146 .1u C148 .1u L28 CK_VDD2 FB 12p C111 .1u C113 .1u I2CD2 I2CD1 C112 .
1 2 3 4 VTT VCC3 CB15 .1u CB18 .1u CM19 1u CT34 1500u C134 1u CT37 1000u CM26 1u CM32 1u CM39 1u CM33 1u CM27 1u CM25 1u CM20 1u CM21 1u CM38 1u CM37 1u CM36 1u CM42 1u CT48 1500u VDDQ CM35 1u A CM28 1u CM31 1u CT38 1500U CT44 1500u CM34 1u CT24 1500u CM40 1u CM18 1u CM30 1u CM29 1u CM23 1u A VCCP V_DIM CM17 1u CM11 1u CM10 1u CM16 1u CM15 1u CM12 1u CM9 1u CM14 1u CM13 1u CB33 .1u CB20 .1u CB28 .1u CB30 .1u CB38 .1u CB23 .1u CB41 .1u CB26 .1u CB34 .
VID0 VID1 VID2 VID3 VID4 4.7K L20 D 1uH C89 1000u 3uH C94 .001u C96 1000u L24 R76 3.3K Q2 NDP6030L G C97 1000u C102 1000u C101 1000u C100 1000u C99 1000u C98 1000u CT30 1000u S C84 1000u 4 VCCP Q4 NDP6030L S A R70 10 DIODE .1u SEN/NC 1 16 GND 17 LGATE 13 PHASE BOOT/NC UGATE 2 V12 OCSET 10 C87 .002u PWGD OVP 19 CT/RT 20 VID0 4 VID1 5 6 8 VID2 R59 (OPT) 0 B C82 .1u V_FB C81 .01u VID3 C83 .1U R61 R60 1.
1 2 3 4 COM1, COM2 AND IR with Bipolar drivers and receivers VCC U1 20 TXD1 RTS1 DTR1 DCD1 RXD1 DSR1 CTS1 RI1 A 16 15 13 19 18 17 14 12 TXD1 RTS1 DTR1 DCD1 RXD1 DSR1 CTS1 RI1 11 VCC VCC1 DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA5 GND VCC2 1 +12V 5 6 8 2 3 4 7 9 10 CN2B 26 27 28 29 30 -12V C32 100p C28 +12V 20 TXD2 RTS2 DTR2 DCD2 RXD2 DSR2 CTS2 RI2 TXD2 RTS2 DTR2 DCD2 RXD2 DSR2 CTS2 RI2 16 15 13 19 18 17 14 12 11 VCC VCC1 DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 DY1 DY2
1 2 3 4 CD_IN1 R18 1 2 3 4 CD_IN C19 4.7K CD_IN_CONN C14 1u CDR AVDD5 1 9 FB 1u CDGND CT17 CB7 10u .1u CT14 CB6 CM2 47u .1u 1u DVDD1 DVDD2 4 7 (1206) 0 (ADI) VDD5 U2 L19 R17 4.7K C18 GND_AUD A CDL (1206) R16 4.7K R7 1u (1206) R9 4.7K DVSS1 DVSS2 L1 25 38 AVDD1 AVDD2 26 42 AVSS1 AVSS2 CM1 CB1 CT3 CT2 1u .1u 10u 10u FB L14 A FB GND_AUD SYNC SDIN_A SDOUT -ACRST BITCLK_A CN3C LIR 26 24 LIL 22 LINE_IN LININ R3 1K C12 1u (1206) R4 1K 4.
1 2 3 4 A A AMR1 B SPEAK AMR_AGND J3 -12V 1 2 +12V B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 AUDIO_MUTE GND MONO_OUT/PC_BEEP RESERVED RESERVED PRIMARY_DN -12V GND +12V GND +5VD AUDIO_PWRDN MONO_PHONE RESERVED RESERVED RESERVED GND +5VDUAL/+5VSB USB_OC GND USB+ USB- A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 R58 C85 B 0 (OPT) PHONE 1u AMR_VCC3 L26 VCC3_SB AMR_VCC 5V_SB L25 AMR_VCC FB FB OVER_C1 USB_D1+ USB_D1- L21 FB VCC3 SDOUT -ACRST SDOUT -ACRST R113 0 (OPT) B12 B13 B14 B15 B16 B17 B18
1 2 3 4 For STR function 5V_SB -RSMRST A 9 14 4 -RSMRST V_DIM 14 5V_SB V3SB 10 6 8 A 5 5V_SB 1 2 3 5V_SB 8 U13C F00 12 D 11 Q C Q 8 74 14 3 2 U15B F02 12 13 1000u 1-2 2-3 DISABLE ENABLE B U15D F02 14 4 V3SB OUT CB44 1000u 2 5V_SB 3 PW_BN GND .1u C163 D P C U16A Q 5 Q 6 R322 C R297 R251 R248 R252 R246 R204 R201 CKE0 CKE1 CKE2 CKE3 CKE4 CKE5 -RSMRST 1.5K R296 74 1 VOUT GND C164 1000u PWRON 11 U13A F00 10u C165 1000u 14 14 3 .
