User`s manual

BIOS Setup
49
CPU AND PCI BUS CONTROL
: Move
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
Menu Level
Item Help
PCI Master 0 WS Write [Enabled]
PCI Delay Transaction [Enabled]
CPU & PCI Bus Contorl
Phoenix - Award WorkstationBIOS CMOS Setup Utility
VLink mode Selection [Mode 1]
VLink 8X Support Enabled
PCI Master 0 WS Write
When Enabled , CPU can write up to four words of data to the PCI write
buffer before CPU must wait for PCI bus cycle to finish. If
Disabled , CPU
must wait after each write cycle until PCI bus signals that it is ready to
receive more data.
Settings: [Enabled, Disabled]
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select
Enabled to support compliance with PCI
specification version 2.1.
Settings: [Enabled, Disabled]