User`s manual

BIOS Setup
43
DRAM CLOCK / DRIVE CONTROL
: Move
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
Menu Level
Item Help
DRAM Timing [Auto By SPD]
Bank Interleave Disabled
Active to Precharge (Tras) 9T
Active to CMD (Trcd) 4T
REF to ACT/REF to REF (Trfc) 15T
ACT(0) to ACT(1) (TRRD) 3T
DRAM Command Rate
[2T Command]
DRAM Clock [By SPD]
DRAM Clock/Drive Contorl
Phoenix - Award WorkstationBIOS CMOS Setup Utility
SDRAM CAS Latency 2.5
Precharge To Active (Trp) 4T
Current FSB Frequency 133MHz
Current DRAM Frequency 200MHz
Current FSB Frequency
This setting specifies the maximum operating frequency of the link's
transmitter clock.
Current DRAM Frequency
This setting specifies the maximum memory clock limit on the system.
DRAM Clock
This item allows you to set the speed of Direct Memory Access (DMA) at
either equal to or one-half of the SYSCLK (system clock signal) speed.
Settings: [By SPD, 100MHz, 133MHz, 166MHz, 200MHz]
Note: While speed is always desirable, choosing the higher setting
may prove to be too fast for some components.