User`s manual

BIOS Setup 3-15
CPU to PCI Post Write
Two options are available: Enabled or Disabled. The default is Enabled, When Enable, data transmission
from CPU to PCI bus are buffered and compensate for the different speed between CPU and PCI bus. If it
is set to Disabled, data transmissions are not buffered and CPU must wait until the data transmission is
complete and then start another transmission cycle.
VLink 8X Support:
Two options are available: Disabled or Enabled. The default setting is Enabled. This item can let you
enable the VLink bus data transfer between northbridge and southbridge.
PCI Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Enabled. The chipset has an
embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.2.
 Back to Advanced Chipset Features Setup Menu:
Memory Hole At 15-16M:
When set to [Enabled], the memory address space at 15M-16M will be reserved for ISA expansion cards
that specifically requires this setting. This makes the memory from 15MB and up unavailable to the
system. Leave this item to its default setting.
Top performance:
This item enables the DRAM performance if there are no compatible issues occurred.
User’s Manual