Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -91- Device 16 Function 5 USB Direct Device Communications Registers
USB Device Communications SRAM Control
Offset 71-70 – SRAM Direct Access Address (0000h)....RW
15-9 Reserved ........................................ always reads 0
8-0 SRAM Direct Access Address..................... def=00h
The valid address range for SRAM 0 is 0 to 011h.
The valid address range for SRAM 1 is 0 to 100h
The valid address range for SRAM 2 is 0 to 100h
Offset 73 – SRAM Direct Access Control (00h)..............RW
7-6 Reserved ........................................ always reads 0
5-4 SRAM Select
There are three SRAMs in the device controller:
00 SRAM 0 - Control Endpoint (18x32).....default
01 SRAM 1 - Bulk Endpoint (129x32)
10 SRAM 2 - Bulk Endpoint (129x32)
11 -reserved-
3-2 Reserved ........................................ always reads 0
1 SRAM Operation Start ................write 1 to trigger
0 SRAM Read / Write Control
0 Read .....................................................default
1 Write
Offset 77-74 – SRAM Direct Access Data (00000000h) .RW
This 32-bit register stores data read from the SRAM or data to
write to the SRAM.
USB Device Communications Power Management Control
Offset 83-80 – PM Capability ........................................... RO
31-0 PM Capability ......... Rx41[1]=0: reads 480A 0001h
............ Rx41[1]=1: reads C9C2 0001h
Offset 84 – PM Capability Status.................................... RW
7-0 PM Capability Status
00 D0 .................................................... default
01 -reserved-
10 -reserved-
11 D3 Hot