Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -90- Device 16 Function 5 USB Direct Device Communications Registers
USB Device Communications MAC Control
Offset 4A – MAC Receiver Enable Delay (00h)..............RW
7-0 MAC Receiver Enable Delay Parameter . def = 00h
Offset 4B – MAC Turnaround Time Delay (09h) ..........RW
7-5 Reserved ........................................ always reads 0
4 Automatic Hardware Reset of Device Address
When USB Bus Reset is Received
0 Enable (auto reset).................................default
1 Disable (no reset)
3-0 USB 2.0 MAC Transmit Turnaround Time
Parameter ........................................... default = 9h
Offset 51 – USB 2.0 MAC Timeout Parameter (5Ah)....RW
This register contains the USB 2.0 receive timeout parameter
in units of bytes. The host controller of a device expecting a
response to a transmission must not timeout the transaction if
the inter-packet delay is between 736 and 816 bit times. The
worst-case round trip delay is 721 bit times.
7-0 USB 2.0 Receive Timeout Parameter ...... def = 5Ah
USB Device Communications PHY Control
Offset 58 – PHY Control 1 (00h) ..................................... RW
7 Test UTM Elastic Buffer Error Control
0 Disable................................................... default
1 Enable
6 Reserved ........................................always reads 0
5 Internal Receive Block During Transmission
0 Disable................................................... default
1 Enable
4 UTM Test Mode Clock Select
0 Use APLL Clock ................................... default
1 Use External Input
3 Internal Loopback Mode
0 Disable................................................... default
1 Enable
2-0 Reserved ........................................always reads 0
Offset 59 – PHY Control 2 (08h) ..................................... RW
7 PHY Auto Power Down
0 Enable (if the port is suspended, the port will
auto power down).................................. default
1 Disable
6 Reserved ........................................always reads 0
5 UTM Autocheck
0 Disable................................................... default
1 Enable
4 Reserved ........................................always reads 0
3 Digital PLL Fast Lock
0 Disable
1 Enable................................................... default
2 Digital PLL Loop Back
0 Disable................................................... default
1 Enable
1-0 Reserved ........................................always reads 0
Offset 5A – High Speed Port Pad Fine Tune (08h)........ RW
7-4 Reserved ........................................always reads 0
3-0 High Speed Port Pad Termination Resistor Fine
Tune ...........................................default = 8h
Offset 5C – PHY Control 3 (53h) .................................... RW
7 Fast Start (DPLL Zero Phase Start Select)
0 ZPS takes 8 bit-times to start................. default
1 ZPS takes 4 bit-times to start
6-4 DPLL Input Data Delay............................ def=101b
3-2 DPLL Track Speed Select........................... def=00b
1-0 DPLL Lock Speed Select ............................ def=11b