Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -60- Device 15 Function 0 Serial ATA Controller Registers
PHY Status Registers
Offset 7C – Internal PHY Status ......................................RO
7-6 Reserved ................................................... default = 0
5 Port2 Auto Check Error Report............. default = 0
4 Port2 Squelch Detector Output
3-2 Reserved ................................................... default = 0
1 Port1 Auto Check Error Report............. default = 0
0 Port1 Squelch Detector Output
Offset 7D – External PHY Status (00h)............................RO
7 External PHY Port2 Receive COMINIT ..... def = 0
6 External PHY Port2 Receive COMWAKE .def = 0
5 External PHY Port1 Receive COMINIT ..... def = 0
4 External PHY Port1 Receive COMWAKE .def = 0
3 Internal PHY Port2 Receive COMINIT...... def = 0
2 Internal PHY Port2 Receive COMWAKE .. def = 0
1 Internal PHY Port1 Receive COMINIT...... def = 0
0 Internal PHY Port1 Receive COMWAKE .. def = 0
Channel Control Registers
Offset 80 – Primary Channel Device Mode Status..........RO
7-0 Primary Channel Parsing FIS Number when in
Device mode.............................................. default = 0
Offset 81 – Secondary Channel Device Mode Status ......RO
7-0 Secondary Channel Parsing FIS Number when in
Device mode.............................................. default = 0
Offset 8B-88 – Primary Channel SG Base Address ........RO
Offset 8F-8C – Secondary Channel SG Base Address ....RO
Power Management Control Registers
Offset C3-C2 – PCI Power Mgmt Capabilities (02h) ..... RO
2-0 Version ...............................................default = 010b
The default value indicates this function complies
with Revision 1.1 of PCI Power Management
Interface Spec.
Offset C5-C4 – PCI Power Mgmt Ctrl / Status..... RW / RO
15-2 Reserved............................................ always reads 0
1-0 Power State
00 D0 .......................................................... default
01 -reserved-
10 -reserved-
11 D3 hot
Miscellaneous Control Registers
Offset D1 – PATA Control (00h)...................................... RO
7-4 Reserved............................................ always reads 0
3 PATA Enable Method
0 PATA will be enabled with Rx49[7]=1 and
SATA function enabled......................... default
1 PATA will be enabled with Rx49[7]=1
2-0 Reserved............................................ always reads 0