Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -57- Device 15 Function 0 Serial ATA Controller Registers
Offset 49 – PATA / SATA Sharing Function Ctrl (82h) RW
7 PATA Function
0 Disable (Rx0E[7] will be 0)
1 Enable...................................................default
6 PATA / SATA Sharing Bus Usage
0 Use PATA
1 Use external PHY ..................................default
5 SATA Ports Master / Slave Configuration
0 Master / Master Configuration
1 Master / Slave Configuration
The default value is set per strap pin PDCS1#.
4-2 Reserved ............................................. always reads 0
1 PATA / SATA Pad Drive Control
0 PATA 2/3 drive strength
1 PATA Full drive strength......................default
0 PATA Slew Rate Control
0 Disable ...................................................default
1 Enable
Offset 4A – SATA External PHY Pad Ctrl I (10h)........ RW
7 VCOMP Internal Latch Control........... RO, def = 0
6-5 VCOMP Output Status (valid only when Bit[4] is
0) ....................................................... RO, def = 0
4 Adjust VCOMP Manually
0 Disable
1 Enable................................................... default
3 SATA Strobe Pad VCOMP Control 1..........def = 0
2 SATA Strobe Pad VCOMP Control 0..........def = 0
1 SATA Data Pad VCOMP Control 1 .............def = 0
0 SATA Data Pad VCOMP Control 0 .............def = 0
Offset 4B – SATA External PHY Pad Ctrl II (0Bh)...... RW
7-4 Reserved..............................................always reads 0
3 SATA Strobe Pad VREF Source Selection
0 Select STBI
1 Select VREF......................................... default
2-0 SATA Strobe Pad Delay Modulation Bits (shared
with PATA) ........................................default = 011b
Offset 4E – PHY Port Error Status Control (00h) ........ RW
7 Enable External PHY Secondary Port Error
Status (2) Output to EEDI Pin ...................... def = 0
6 Enable External PHY Secondary Port Error
Status (1) Output to EEDI Pin ...................... def = 0
5 Enable External PHY Primary Port Error Status
(2) Output to EEDI Pin..................................def = 0
4 Enable External PHY Primary Port Error Status
(1) Output to EEDI Pin..................................def = 0
3 Enable Internal PHY Secondary Port Error
Status (2) Output to EEDI Pin ...................... def = 0
2 Enable Internal PHY Secondary Port Error
Status (1) Output to EEDI Pin ...................... def = 0
1 Enable Internal PHY Primary Port Error Status
(2) Output to EEDI Pin..................................def = 0
0 Enable Internal PHY Primary Port Error Status
(1) Output to EEDI Pin..................................def = 0