Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -56- Device 15 Function 0 Serial ATA Controller Registers
Offset 44 – Miscellaneous Control I (0Eh) ......................RW
7 Reserved ............................................. always reads 0
6 Master Read Cycle IRDY# Wait States ....... def = 0
5 Master Write Cycle IRDY# Wait States ...... def = 0
4 Reserved ............................................. always reads 0
3 Bus Master IDE Status Register Read Retry
0 Disable
1 Enable...................................................default
2 Change Drive to Clear all FIFO Internal States
0 Disable
1 Enable...................................................default
1 Split 2 Channel Request
0 Disable
1 Enable...................................................default
0 Reserved ............................................. always reads 0
Offset 45 – Miscellaneous Control II (AF) ......................RW
7 Sub Class (Rx0A) Write Protect
0 Rx0A Write Enable
1 Rx0A Write Disable..............................default
6 Clock Gating
0 Enable ....................................................default
1 Disable
5 Latency Timer
0 Disable
1 Enable...................................................default
Set to 1 only when GNT is deasserted, to improve
performance.
4 Interrupt Line (Rx3C) Write Protect
0 Rx3C Write Enable ................................default
1 Rx3C Write Disable
3 Memory Read Multiple Command
0 Disable
1 Enable...................................................default
2 Memory Write and Invalidate Command
0 Disable
1 Enable...................................................default
1 Pri Channel Read DMA Flush Data After Intrpt
0 Disable
1 Enable...................................................default
0 Sec Channel Read DMA Flush Data After Intrpt
0 Disable
1 Enable...................................................default
Offset 46 – Miscellaneous Control III (00h) ................... RW
7-3 Reserved..............................................always reads 0
5 IRQ Asserted When Device Is Hot-Plugged
0 Disable................................................... default
1 Enable
4 Reserved (Do Not Program) ....................default = 0
3 Reserved..............................................always reads 0
2 PLL Reset
0 Disable................................................... default
1 Enable
Occurs when external PCI clock is stopped.
1 Improve PIO Performance
0 On.......................................................... default
1 Off
0 Mask PCI Bus Input Floating Signal (Vector
Mode and Test Only)
0 Disable................................................... default
1 Enable
Offset 48 – PHY Wakeup Request Control (00h) .......... RW
7-4 Reserved..............................................always reads 0
3 External PHY Port 2 Wakeup Request........def = 0
2 External PHY Port 1 Wakeup Request........def = 0
1 Internal PHY Port 2 Wakeup Request.........def = 0
0 Internal PHY Port 1 Wakeup Request.........def = 0
The internal request is triggerred by the rising edge of each bit
written.