Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -43- Legacy I/O Registers
Register Descriptions
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only. Detailed descriptions of the
actions and programming of these registers are included in
numerous industry publications (duplication of that
information here is beyond the scope of this document). All
of these registers reside in I/O space.
Port 61 - Misc Functions & Speaker Control................. RW
7 SERR# Status .......................................................RO
0 SERR# has not been asserted ................ default
1 SERR# was asserted by a PCI agent
Note: This bit is set when the PCI bus SERR# signal
is asserted. Once set, this bit may be cleared
by setting bit-2 of this register. Bit-2 should
be cleared to enable recording of the next
SERR# (i.e., bit-2 must be set to 0 to enable
this bit to be set).
6 IOCHK# Status ....................................................RO
0 IOCHK# has not been asserted.............. default
1 IOCHK # was asserted by an ISA agent
Note: This bit is set when the ISA bus IOCHCK#
signal is asserted. Once set, this bit may be
cleared by setting bit-3 of this register. Bit-3
should be cleared to enable recording of the
next IOCHCK# (i.e., bit-3 must be set to 0 to
enable this bit to be set). IOCHCK# generates
NMI to the CPU if NMI is enabled.
5 Timer/Counter 2 Output .....................................RO
This bit reflects the output of Timer/Counter 2
without any synchronization.
4 Refresh Detected...................................................RO
This bit toggles on every rising edge of the ISA bus
REFRESH# signal.
3 IOCHK# Enable
0 Enable (see bit-6 above) ........................ default
1 Disable (force IOCHCK# inactive and clear
any “IOCHCK# Active” condition in bit-6)
2 SERR# Enable
0 Enable (see bit-7 above) ........................ default
1 Disable (force SERR# inactive and clear any
“SERR# Active” condition in bit-7)
1 Speaker Enable
0 Disable................................................... default
1 Enable Timer/Ctr 2 output to drive SPKR pin
0 Timer/Counter 2 Enable
0 Disable................................................... default
1 Enable Timer/Counter 2
Port 92h - System Control................................................ RW
7-2 Reserved ........................................always reads 0
1 A20 Address Line Enable
0 A20 disabled / forced 0 (real mode) ...... default
1 A20 address line enabled
0 High Speed Reset
0 Normal
1 Briefly pulse system reset to switch from
protected mode to real mode