Product specifications
VT8237R Data Sheet
Revision 2.06 December 15, 2004 -36- Register Overview
Device 17 Function 0 Registers – Bus Control & Power
Management
Configuration Space Bus Control & PM Header Registers
Offset
Confi
g
uration S
p
ace Header Default Acc
1-0 Vendor ID
1106
RO
3-2 Device ID
3227
RO
5-4 Command
0087 RW
7-6 Status
0200 WC
8 Revision ID
nn
RO
9 Programming Interface 00 RO
A Sub Class Code
01
RO
B Base Class Code
06
RO
C -reserved- (cache line size) 00 —
D -reserved- (latency timer) 00 —
E Header Type
80
RO
F Built In Self Test (BIST) 00 RO
10-27 -reserved- (base address registers) 00 —
28-2B -reserved- (unassigned) 00 —
2D-2C Sub Vendor ID 00 RO
2F-2E Sub Device ID 00 RO
30-33 -reserved- (expan. ROM base addr) 00 —
34-3B -reserved- (unassigned) 00 —
3C -reserved- (interrupt line) 00 —
3D -reserved- (interrupt pin) 00 —
3E -reserved- (min gnt) 00 —
3F -reserved- (max lat) 00 —
Configuration Space PCI-to-ISA Bridge-Specific Registers
Offset
ISA Bus Control Default Acc
40 ISA Bus Control 00 RW
41 BIOS ROM Decode Control 00 RW
42 Line Buffer Control 00 RW
43 Delay Transaction Control 00 RW
44 INTE / INTF Routing 00 RW
45 INTG / INTH Routing 00 RW
46 INT Control 00 RW
47 -reserved- 00 —
48 Read Pass Write Control 00 RW
49 CCA Control 00 RW
4A LPC Firmware Memory Control 1 00 RW
4B LPC Firmware Memory Control 2 00 RW
Offset
Miscellaneous Control Default Acc
4C IDE Interrupt Routing 00 RW
4D Miscellaneous Control 00 RW
4E Internal RTC Test Mode 00 RW
4F PCI Bus & CPU Interface Control 00 RW
Offset
Function Control Default Acc
50 Function Control 1 00 RW
51 Function Control 2
0C
RW
Offset
Serial IR
Q,
LPC & PC/PCI Control Default Acc
52 Serial IRQ & LPC Control 00 RW
53 PC/PCI DMA Control 00 RW
Offset
Plu
g
and Pla
y
Control Default Acc
54 PCI Interrupt Polarity 00 RW
55 PnP Routing for PCI INTA 00 RW
56 PnP Routing for PCI INTB-C 00 RW
57 PnP Routing for PCI INTD 00 RW
Offset
GPIO and Miscellaneous Control Default Acc
58 Miscellaneous Control 0
40
RW
59 Miscellaneous Control 1 00 RW
5A DMA Bandwidth Control 00 RW
5B Miscellaneous Control 2 00 RW
Offset
Pro
g
rammable Chi
p
Select Control Default Acc
5D-5C PCS0# I/O Port Address 0000 RW
5F-5E PCS1# I/O Port Address 0000 RW
61-60 PCS2# I/O Port Address 0000 RW
63-62 PCS3# I/O Port Address 0000 RW
64 PCS[1-0]# I/O Port Address Mask 00 RW
65 PCS[3-2]# I/O Port Address Mask 00 RW
66 Programmable Chip Select Control 00 RW
67 Output Control
04
RW
68 HPET Control 00 RW
6B-69 HPET Memory Base Address 000000 RW
Offset
Miscellaneous Default Acc
6C ISA Positive Decoding Control 1 00 RW
6D ISA Positive Decoding Control 2 00 RW
6E ISA Positive Decoding Control 3 00 RW
6F ISA Positive Decoding Control 4 00 RW
71-70 Sub Vendor ID Backdoor 00 RW
73-72 Sub Device ID Backdoor 00 RW
70-73 -reserved- 00 —
74 PCI I/O Cycle Control 00 RW
75-78 -reserved- 00 —
79-7B Reserved for Test (Do Not Program) 00 RW
7C I/O Pad Control 00 RW
7D-7F -reserved- 00 —