Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -23- Pin Descriptions
Strap Pin Descriptions
Strap Pins
(External pullup / pulldown straps are required to select “H” / “L”)
Strap Pins for VT8237R Configuration
Signal Pin# Function Description Status Bit Note
SPKR AF8 CPU
Frequency
Strapping
L: Enable CPU Frequency Strapping
H: Disable CPU Frequency Strapping
Default setting: Disable
-
ACSDOUT U2 Auto Reboot L: Enable Auto Reboot
H: Disable Auto Reboot
Default setting: Disable
-
EEDI A12 Eliminate
External LAN
EEPROM
L: Disable. Use external EEPROM
H: Enable. Do not use external
EEPROM
Default setting: Disable
-
ACSYNC T2 LPC FWH
Command
L: Enable LPC FWH Command
H: Disable LPC FWH Command
Default setting: Disable
-
PDCS1# V22 SATA Master
/ Slave Mode
L: SATA Master Slave Mode
H: SATA Master Master Mode
Strapping low when using external PHY
D15F0
Rx49[5]
PDDACK# V24 External
SATA PHY
L: Enable External SATA PHY
H: Disable External SATA PHY
D15F0
Rx49[6]
PCISTP# /
GPO6
AD6 Reserved Reserved for future use. Must be strapped
high
-
Strap Pins for North Bridge (“NB”) Configuration
PDCS3# V23 NB
Configuration
PDCS3# signal state is reflected on signal pin
VD7 during power up for North Bridge
configuration.
-
Check the North Bridge DS
for details
PDA2 W24 NB
Configuration
PDA2 signal state is reflected on signal pin
VD6 during power up for North Bridge
configuration.
-
Check the North Bridge DS
for details -
PDA1 V25 NB
Configuration
PDA1 signal state is reflected on signal pin
VD5 during power up for North Bridge
configuration.
-
Check the North Bridge DS
for details -
GPIOD /
PCGNTB
AC6 NB
Configuration
GPIOD/PCGNTB signal state is reflected on
signal pin VD3 during power up for North
Bridge configuration.
-
Check the North Bridge DS
for details -
GPIOB /
PCREQB
AD5 NB
Configuration
GPIOB/PCREQB signal state is reflected on
signal pin VD2 during power up for North
Bridge configuration.
-
Check the North Bridge DS
for details -
PDA0,
GPIOA /
PCREQA,
GPIOC /
PCGNTA
W23
AE5
AF5
NB
Configuration
PDA0, GPIOA/PCREQA and
GPIOC/PCGNTA signal states are reflected
on signal pins VD4, VD1 and VD0 during
power up for North Bridge configuration.
-
Check the North Bridge DS
for details -
Summary of Internal Pull-Up / Pull-Down Resistor Implementation
Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0]
Internal Pulldowns are present on all LAN pins