Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -22- Pin Descriptions
Clocks, Resets, Power Status, Power and Ground Pin Descriptions
Resets, Clocks, and Power Status
Signal Name Pin # I/O Signal Description
PWRGD
AC5 I Power Good. Connected to the Power Good signal on the Power Supply. Internal logic
powered by VBAT.
PWROK#
AF1 O Power OK. Internal logic powered by VSUS33.
PCIRST#
R1 O PCI Reset. Active low reset signal for the PCI bus. The VT8237R will assert this pin
during power-up or from the control register.
OSC
AB8 I Oscillator. 14.31818 MHz clock signal used by the internal Timer.
RTCX1
AE4 I RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is used for the
internal RTC and power-well power management logic and is powered by VBAT.
RTCX2
AF3 O RTC Crystal Output: 32.768 KHz crystal output. Internal logic powered by VBAT.
TEST
AE9 I
Test.
TPO
AF9 O Test Pin Output. Output pin for test mode.
Power and Ground
Signal Name Pin # I/O Signal Description
VCC33
(see pin list) P
I/O Power. 3.3V ±5%
VCC
(see pin list) P
Core Power. 2.5V ±5%. This supply is turned on only when the mechanical switch on
the power supply is turned on and the PWRON signal is conditioned high.
GND
(see pin list) P Ground. Connect to primary motherboard ground plane.
VSUS33
AA4, AB4-6 P Suspend Power. 3.3V ±5%. Always available unless the mechanical switch of the
power supply is turned off. If the “soft-off” state is not implemented, then this pin can be
connected to VCC33. Signals powered by or referenced to this plane are: PWRGD,
RSMRST#, PWRBTN#, SMBCK1/2, SMBDT1/2, GPO0, SUSA# / GPO1, SUSB# /
GPO2, SUSC#, SUSST1# / GPO3, SUSCLK / GPO4, GPI1, GPI2 / EXTSMI#, GPI3 /
RING#, GPI4 / LID, GPI5 / BATLOW#, GPI6 / PME#, SMBALRT#
VSUS25
T4, U4 P Suspend Power. 2.5V ±5%.
VSUSUSB
C24 P USB Suspend Power. 2.5V ±5%.
VBAT
AF4 P RTC Battery. Battery input for internal RTC (RTCX1, RTCX2)
VLVREF
H22 P V-Link Voltage Reference. 0.9V ±5% for 4x transfers and 0.625V ±5% for 8x transfers.
VLCOMP
J22 AI
V-Link Compensation.
VCCVK
(see pin list) P
V-Link Compensation Circuit Voltage. 2.5V ±5%
MIIVCC
D9, E9-11 P
Refer to “LAN Controller – Media Independent Interface (MII)” on page 13 for
details.
MIIVCC25
D12. E12 P LAN MII Suspend Power. 2.5V ±5%.
LANVCC
E7 P LAN Power. 2.5V ±5%. Power for LAN. Connect to VCC through a ferrite bead.
LANGND
E6 P LAN Ground. Connect to GND through a ferrite bead.
USBVCC
(see pin list) P USB 2.0 Differential Output Power. 3.3V ±5%. Power for USB differential outputs
(USBP0+, P0–, P1+, P1–, P2+, P2–, P3+, P3–, P4+, P4–, P5+, P5–). Connect to VSUS33
through a ferrite bead.
USBGND
(see pin list) P USB 2.0 Differential Output Ground. Connect to GND through a ferrite bead.
VCCUPLL
A23, B23 P USB 2.0 PLL Analog Voltage. 2.5V ±5%. Connect to VCC through a ferrite bead.
GNDUPLL
C23, D23 P USB 2.0 PLL Analog Ground. Connect to GND through a ferrite bead.
PLLVCC
T22 P PLL Analog Power. 2.5V ±5%. Connect to VCC through a ferrite bead.
PLLGND
U22 P PLL Analog Ground. Connect to GND through a ferrite bead.
SDVREF
AC19 P Parallel ATA Secondary Data Channel Voltage Reference. 0.9V†
SDCOMP
AB21 AI Parallel ATA Secondary Data Channel Disk Compensation. 360Ω 1% to ground
†Created by a resistive voltage divider of 1KΩ 1% to 3.3V and 383Ω 1% to ground (see Design Guide)