Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -12- Pin Descriptions
PCI Bus Pin Descriptions
PCI Bus Interface
Signal Name Pin # I/O Signal Description
AD[31:0]
(see pin
list)
IO Address / Data Bus. Multiplexed address and data. The address is driven with FRAME#
assertion and data is driven or received in following cycles.
CBE[3:0]#
M3, L4,
C1, E2
IO Command / Byte Enable. The command is driven with FRAME# assertion. Byte
enables corresponding to supplied or requested data are driven on following clocks.
DEVSEL#
H2 IO Device Select. The VT8237 asserts this signal to claim PCI transactions through positive
or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8237-
initiated transaction and is also sampled when decoding whether to subtractively decode
the cycle.
FRAME#
J1 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that
one more data transfer is desired by the cycle initiator.
IRDY#
J2 IO Initiator Ready. Asserted when the initiator is ready for data transfer.
TRDY#
H1 IO Target Ready. Asserted when the target is ready for data transfer.
STOP#
K4 IO Stop. Asserted by the target to request the master to stop the current transaction.
SERR#
C2 I System Error. SERR# can be pulsed active by any PCI device that detects a system error
condition. Upon sampling SERR# active, the VT8237 can be programmed to generate an
NMI to the CPU.
PERR#
C3
－
Parity Error. PERR#, sustained tri-state, is only for the reporting of data parity errors
during all PCI transactions except for a Special Cycle.
PAR
F4 IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
INTA#
INTB#
INTC#
INTD#
INTE# / GPI12,
/ GPO12,
INTF# / GPI13,
/ GPO13,
INTG# / GPI14,
/ GPO14,
INTH# / GPI15,
/ GPO15
A4
B4
B5
C4
D4
E4
A3
B3
I PCI Interrupt Request. The INTA# through INTD# pins are typically connected to the
PCI bus INTA#-INTD# pins per the table below. INTE-H# are enabled by setting Device
17 Function 0 Rx5B[1] = 1 and RxE4[4] = 0. BIOS settings must match the physical
connection method.
INTA#
INTB# INTC# INTD#
PCI Slot 1 INTA# INTB# INTC# INTD#
PCI Slot 2 INTB# INTC# INTD# INTE#
PCI Slot 3 INTC# INTD# INTE# INTF#
PCI Slot 4 INTD# INTE# INTF# INTG#
PCI Slot 5 INTE# INTF# INTG# INTH#
PCI Slot 6 INTF# INTG# INTH# INTA#
REQ5# / GPI7,
REQ4#,
REQ3#,
REQ2#,
REQ1#,
REQ0#
R3
P3
D5
C5
B6
A5
I PCI Request. These signals connect to the VT8237 from each PCI slot (or each PCI
master) to request the PCI bus. To use pin R3 as REQ5#, Function 0 RxE4 must be set to
1 otherwise this pin will function as General Purpose Input 7.
GNT5# / GPO7,
GNT4#,
GNT3#,
GNT2#,
GNT1#,
GNT0#
R2
R4
E5
C6
D6
A6
O PCI Grant. These signals are driven by the VT8237 to grant PCI access to a specific PCI
master. To use pin R2 as GNT5#, Function 0 RxE4 must be set to 1 otherwise this pin
will function as General Purpose Output 7.
PCIRST#
R1 O PCI Reset. This signal is used to reset devices attached to the PCI bus.
PCICLK
R23 I PCI Clock. This signal provides timing for all transactions on the PCI Bus.
PCKRUN#
AB7 IO PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped
(high) or running (low). The VT8237 drives this signal low when the PCI clock is running
(default on reset) and releases it when it stops the PCI clock. External devices may assert
this signal low to request that the PCI clock be restarted or prevent it from stopping.
Connect this pin to ground using a 100 Ω resistor if the function is not used. Refer to the
“PCI Mobile Design Guide” and VIA PT400 or K8M400 Design Guides for more details.