Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -11- Pin Descriptions
CPU, APIC and CPU Control Pin Descriptions
CPU Interface
Signal Name Pin # I/O Signal Description
A20M#
U26 OD A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation.
Logical combination of the A20GATE input (from internal or external keyboard controller)
and Port 92 bit-1 (Fast_A20).
FERR#
U24 I Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the
CPU. Internally generates interrupt 13 if active. Input voltage swing is programmable to
1.5V or 2.5V by Device 17 Function 0 Rx67[2].
IGNNE#
T24 OD Ignore Numeric Error. This pin is connected to the CPU “ignore error” pin.
INIT#
R26 OD Initialization. The VT8237R asserts INIT# if it detects a shut-down special cycle on the
PCI bus or if a soft reset is initiated by the register
INTR
T25 OD CPU Interrupt. INTR is driven by the VT8237R to signal the CPU that an interrupt
request is pending and needs service.
NMI
T26 OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The
VT8237R generates an NMI when PCI bus SERR# is asserted.
SLP#
V26 OD Sleep. Used to put the CPU to sleep.
SMI#
U25 OD System Management Interrupt. SMI# is asserted by the VT8237R to the CPU in
response to different Power-Management events.
STPCLK#
R24 OD Stop Clock. STPCLK# is asserted by the VT8237R to the CPU to throttle the processor
clock.
Note: Connect each of the above signals to 150 Ω pullup resistors to VCC_CMOS (see Design Guide).
CPU Speed Control Interface
Signal Name Pin # I/O Signal Description
VGATE / GPI8
/ GPO8
AC9 I Voltage Gate. Signal from the CPU voltage regulator. High indicates the voltage regulator
output is stable. This pin performs the VGATE function if Device 17 Function 0 RxE5[4]
= 1 and E4[3] = 0.
VIDSEL / GPI28
/ GPO28
AC8 OD Voltage Regulator ID Select. Connected to the CPU voltage regulator. Low selects the
voltage ID from the CPU; high selects a different fixed voltage ID (the lower voltage used
for CPU deep sleep mode). This pin performs the VIDSEL function if Device 17 Function
0 RxE5[3] = 0.
VRDSLP / GPI29
/ GPO29
AB9 OD Voltage Regulator Deep Sleep. Connected to the CPU voltage regulator. High selects
the proper voltage for deep sleep mode. This pin performs the VRDPSLP function if
Device 17 Function 0 RxE5[3] = 0.
GHI# / GPI22
/ GPO22
R22 OD CPU Speed Select. Connected to the CPU voltage regulator, used to select high speed (L)
or low speed (H). This pin performs the GHI# function if Device 17 Func 0 RxE5[3] = 0.
DPSLP# / GPI23
/ GPO23
P21 OD CPU Deep Sleep. This pin performs the DPSLP# function if Device 17 Function 0
RxE5[3] = 0.
CPUMISS / GPI17 Y1 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High
indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of
this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and
GPI17 at the same time.
AGPBZ# / GPI6 AD10 I AGP Busy. Low indicates that an AGP master cycle is in progress (CPU speed transitions
will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.
Advanced Programmable Interrupt Controller (APIC) Interface
Signal Name Pin # I/O Signal Description
APICD1 / GPIO11 T23 O Internal APIC Data 1. Device 17 Function 0 Rx58[6] = 1 & APIC Rx3[0] = 0
APICD0 / GPIO10 R25 O Internal APIC Data 0. Device 17 Function 0 Rx58[6] = 1 & APIC Rx3[0] = 0
APICCLK / GPI19 U23 I Internal APIC Clock. Device 17 Function 0 Rx58[6] = 1 & APIC Rx3[0] = 0