Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -167- Functional Descriptions
3) Generic Global Events defined in the Global Status and
Global Enable registers. These registers are mainly used
for SMI:
• PCI Bus Clock Run Resume
• Primary Interrupt Occurance
• GP0 and GP1 Timer Time Out
• Secondary Event Timer Time Out
• Occurrence of Primary Events
(defined in the Primary Activity Status and Primary
Activity Enable registers)
• Legacy USB accesses (keyboard and mouse)
- Software SMI
System and Processor Resume Events
Depending on the system suspend state, different features can
be enabled to resume the system. There are two classes of
resume events:
a) VSUS-based events. Event logic resides in the
VSUS plane and thus can resume the system from
any suspend state. Such events include PWRBTN#,
RI#, BATLOW#, LID, SMBus resume event, RTC
alarm, EXTSMI#, and GP1 (EXTSMI1#).
b) VCC-Based Events. Event logic resides in the VCC
plane and thus can only resume the system from the
POS state. Such events include the ACPI PM timer,
USB resume, and EXTSMIn#.
Figure 6. System Block Diagram Using the PT800 North Bridge
HCLK
GCLK
Host CPU
CPU
Bus
CKE#
Memory Bus
SMBus
LPC
North
Bridge
DDR
SDRAM
3D
Graphics
Controller
AGP Bus
PCISTP#
GPIO and ACPI Events
RAID / Serial ATA
GCKRUN#
PCI Bus
8 Ports USB 2
AC97 Audio / Mode
m
Power Plane & Peripheral Control
VT8237R
South
Bridge
Ke
y
board / Mouse
CPUSTP#
Clock
Generator
MCL
K
HCLK
GCLK
PCLK
SMI# / STPCLK#
SUSCLK,
SUSST1#
SMIACT#
Module ID
PHY
MII
10 / 100BaseT Lan
IDE / Parallel ATA
V-Link
Interface
PCKRUN#
PCLK