Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -165- Functional Descriptions
Processor Bus States
The VT8237R supports the complete set of C0 to C3
processor states as specified in the Advanced Configuration
and Power Interface (ACPI) specification (and defined in
ACPI I/O space Registers 10-15):
C0: Normal Operation
C1: CPU Halt (controlled by software).
C2: Stop Clock. Entered when the Processor Level 2
register (PMIO Rx14) is read. The STPCLK# signal
is asserted to put the processor in the Stop Grant
State. The CPUSTP# signal is not asserted so that
host clocks remain running. To exit this state, the
chip negates STPCLK#.
C3: Suspend. Entered when the Processor Level 3
register (PMIO Rx15) is read. In addition to
STPCLK# assertion as in the C2 state, the SUSST1#
(suspend status 1) signal is asserted to tell the north
bridge to switch to “Suspend DRAM Refresh” mode
based on the 32KHz suspend clock (SUSCLK)
provided by the VT8237R. If the Host Stop bit is
enabled, then CPUSTP# is also asserted to stop clock
generation and put the CPU into Stop Clock State.
To exit this state, the chip negates CPUSTP# and
allows time for the processor PLL to lock. Then the
SUSST1# and STPCLK# signals are negated to
resume to normal operation.
During normal operation, two mechanisms are provided to
modulate CPU execution and control power consumption by
throttling the duty cycle of STPCLK#:
a. Setting the Throttle Enable bit to 1, the duty
cycle defined in Throttle Duty Cycle (PMIO
Rx10) is used.
b. THRM# pin assertion enables automatic clock
throttling with duty cycle pre-configured in
THRM# Duty Cycle (PCI configuration Rx4C).
System Suspend States and Power Plane Control
There are three power planes inside the VT8237R. The first
power plane (VSUS33) is always on unless turned off by the
mechanical switch. The second power plane (VCC) is
controlled by chip output SUSC# (also called “PSON”). The
third plane (VCCRTC) is powered by the combination of the
VSUS33 and the external battery (VBAT) for the integrated
real time clock. Most of the circuitry inside the VT8237R is
powered by VCC. The amount of logic powered by VSUS33
is very small; its main function is to control the supply of
VCC and other power planes. VCCRTC is always on unless
both the mechanical switch and VBAT are removed.
The VT8237R supports multiple system suspend states by
configuring the SLP_TYP field of ACPI I/O space register
Rx4-5:
a) POS (Power On Suspend): Most devices in the
system remain powered. The host bus is put into an
equivalent of the C3 state. In particular, the CPU is
put into the Stop Grant State or Stop Clock State
depending on the setting of the Host Stop bit.
SUSST1# is asserted to tell the north bridge to switch
to “Suspend DRAM Refresh” mode based on the
32KHz SUSCLK provided by the VT8237R. As to
the PCI bus, setting the PCLK Run bit to 0 enables
the CLKRUN protocol defined in the PCI Mobile
Design Guide. That is, the PCKRUN# pin will be
de-activated after the PCI bus is idle for 26 clocks.
Any PCI bus masters including the north bridge may
resume PCI clock operation by pulling the
PCKRUN# pin low. During the PCKRUN# de-
activation period, the PCISTP# pin may be activated
to disable the output of the PCI clock generator if the
PCI_STP bit is enabled. When the system resumes
from POS, the VT8237R can optionally resume
without resetting the system, can reset the processor
only, or can reset the entire system. When no reset is
performed, the chip only needs to wait for the clock
synthesizer and processor PLL to lock before the
system is resumed, which typically takes 20ms.
b) STR (Suspend to RAM): Power is removed from
most of the system except the system DRAM. Power
is supplied to the suspend refresh logic in the north
bridge (e.g., VSUS25 or equivalent) and the suspend
logic of the VT8237R (VSUS33).
c) STD (Suspend to Disk, also called Soft-off): Power
is removed from most of the system except the
suspend logic of VT8237R (VSUS33).
d) Mechanical Off: This is not a suspend state. All
power in the system is removed except the RTC
battery.