Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -158- Device 18 Function 0 LAN Registers
Offset 70 – MII Management Port Command (00h)......RW
7 MII (PHY) Auto Polling
0 Disable ...................................................default
1 Enable (polling interval determined by
Rx6C[7:6] )
6 PHY Read
Every time this bit is set to one, the Phy is read once.
The address read is determined by Rx71[4:0] and the
data is stored in Rx73-72.
0 Disable ...................................................default
1 Enable
5 PHY Write
Every time this bit is set to one, the PHY is written
once. The address written is determined by
Rx71[4:0] and the value in Rx73-72 will be written to
the PHY.
0 Disable ...................................................default
1 Enable
4 PHY Direct Programming Mode
0 Disable (bits 3-0 are ignored, see bits 6-5)...def
1 Enable (bits 6-5 are ignored, see bits 2-0)
3 MDIO Output Enable Indicator
2 Phy Direct Programming Write Data Out
During direct programming (write), the value in this
bit is written to the Phy every time bit-0 of this
register (the “clock”) toggles.
1 Phy Direct Programming Read Data In ............RO
During direct programming (read), every time the
“clock” (bit-0) toggles, the value from the Phy is
stored in this bit.
0 Phy Direct Programming Clock
This bit acts as the clock during direct reads from and
direct writes to the Phy.
Offset 71 – MII Management Port Address (81h)..........RW
7 Polling Status
0 Polling mechanism is busy (polling can’t be
initiated)
1 Polling mechanism is idle (polling can be
initiated) ................................................default
6 Polling Type
0 Poll One Cycle .......................................default
1 Auto polling – close the pause function at bit-5
5 Polling Complete
0 Polling not complete ..............................default
1 Polling complete (auto polling data ready)
4-0 MII Management Port Address Bits 4-0..def = 01h
This field contains the address of the PHY register to
be read or written.
Offset 73-72 – MII Management Port Data Data...........RW
After a Phy read, the data read from the PHY is stored in this
register. For writes to the Phy, the data to be written is placed
in this register.
Offset 74 – EEPROM Command / Status (00h)............. RW
7 EEPROM Program Complete...............RO, def = 0
Set when EEPROM loading is complete.
6 EEPROM Embedded Program Enable........def = 0
When this bit is set, configuration data (in Rx6E, 6F,
74, 78, 79, 7A, and 7B) will start to be programmed
into the EEPROM.
5 Dynamically Reload EEPROM Content ...... def = 0
When this bit toggles, the Ethernet ID (Rx5-0) is
reloaded from EEPROM.
4 EEPROM Direct Program Mode
0 Disable................................................... default
1 Enable (see bits 3-0)
3 EEPROM Direct Programming Chip Select
This bit must be set to allow proramming of the
EEPROM using bits 2-0
2 EEPROM Direct Programming Clock
This bit acts as the clock for direct programming of
the EEPROM.
1 EEPROM Direct Programming Write Data
During direct programming (write), the value in this
bit is presented to the EEPROM Data In pin and
written to the EEPROM every time bit-2 of this
register (the “clock”) toggles.
0 EEPROM Direct Programming Read Data...... RO
During direct programming (read), every time bit-2
of this register (the “clock”) toggles, the value on the
EEPROM Data Out pin is stored in this bit.
Offset 78 – EEPROM Control (00h) ............................... RW
7 EEPROM Embedded & Direct Programming
0 Disable (EEPROM cannot be programmed)def
1 Enable (allow EEPROM to be programmed)
6 Extension Clock
0 Disable................................................... default
1 Enable (the clock to the EEPROM is sent prior
to the start of data to allow more time for the
EEPROM to return to the ready state)
5-0 Reserved ........................................always reads 0