Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -122- I/O Space Power Management Registers
Processor Power Management Registers
I/O Offset 13-10 - Processor & PCI Bus Control ...........RW
31-12 Reserved ........................................ always reads 0
11 Disable PCISTP# When PCKRUN# is Deasserted
0 Enable ....................................................default
1 Disable
10 PCI Bus Clock Run Without Stop
0 PCKRUN# is always asserted................default
1 PCKRUN# will be de-activated after the PCI
bus is idle for 26 clocks
9 Host Clock Stop
This bit controls whether CPUSTP# is asserted in C3
and S1 states. Normally CPUSTP# is not asserted in
C3 and S1 states, only STPCLK# is asserted.
0 CPUSTP# will not
be asserted in C3 and S1
states (only STPCLK# is asserted).........default
1 CPUSTP# will
be asserted in C3 and S1 states
8 Assert SLP# for Processor Level 3 Read
This bit controls whether SLP# is asserted in C3
state.
0 SLP# is not asserted in C3 state .............default
1 SLP# is asserted in C3 state
Used with Intel CPUs only.
7 Lower CPU Voltage During C3 / S1
This bit controls whether the CPU voltage
is lowered
when in C3/S1 state. The voltage is lowered using
the VRDSLP signal to the voltage regulator. PMIO
RxE5[3] must be 0 to enable the voltage change
function. Bits 8 and 9 of this register must also be set
to 1.
0 Disable (normal voltage during C3/S1) .......def
1 Enable (lower voltage during C3/S1)
6-5 Reserved ........................................ always reads 0
4 Throttling Enable
Setting this bit starts clock throttling (modulating the
STPCLK# signal) regardless of the CPU state. The
throttling duty cycle is determined by bits 3-0 of this
register.
3-0 Throttling Duty Cycle
This field determines the duty cycle of the STPCLK#
signal when the system is in throttling mode
("Throttling Enable" bit of this register set to one).
The duty cycle indicates the percentage of
performance (the lower the percentage, the lower the
performance and the higher the power savings). If
the Throttling Timer Width (Function 0 Rx8D[6-5])
is set to 3-bit width, bit-0 of this field should be set to
0 (and the performance increment will be 12.5%). If
the Throttling Timer Width is set to 2-bit width, bits
1-0 of this field should be set to 0 (and the
performance increment will be 25%).
Throttling Timer Width
4-Bit
3-Bit 2-Bit
0000 -reserved- -reserved- -reserved-
0001 6.25% -reserved- -reserved-
0010 12.50% 12.50% -reserved-
0011 18.75% -reserved- -reserved-
0100 25.00% 25.00% 25.00%
0101 31.25% -reserved- -reserved-
0110 37.50% 37.50% -reserved-
0111 43.75% -reserved- -reserved-
1000 50.00% 50.00% 50.00%
1001 56.25% -reserved- -reserved-
1010 62.50% 62.50% -reserved-
1011 68.75% -reserved- -reserved-
1100 75.00% 75.00% 75.00%
1101 81.25% -reserved- -reserved-
1110 87.50% 87.50% -reserved-
1111 93.75% -reserved- -reserved-
I/O Offset 14 - Processor Level 2...................................... RO
7-0 Level 2 ........................................always reads 0
Reads from this register put the processor into the
Stop Grant state (the VT8237R asserts STPCLK# to
suspend the processor). Wake up from Stop Grant
state is by interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this register
have no effect.
I/O Offset 15 - Processor Level 3...................................... RO
7-0 Level 3 ........................................always reads 0
Reads from this register put the processor in the C3
clock state with the STPCLK# signal asserted. If
Rx10[9] = 1 then the CPU clock is also stopped by
asserting CPUSTP#. Wakeup from the C3 state is by
interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this register
have no effect.