Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -5- Overview
The VT8237R also enhances the functionality of standard integrated peripherals. The integrated interrupt controller supports both
edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to
standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT8237R supports delayed transactions and remote
power management so that slower internal ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to
allow concurrent operation without causing deadlock even in a PCI-to-PCI bridge environment. The chip also includes eight
levels (doublewords) of line buffers from the PCI bus to internal ISA bus devices to further enhance overall system performance.
The high performance Serial ATA RAID Controller in the VT8237R supports RAID Level 0, RAID Level 1, RAID Level 0+1 and
JBOD. The internal PCI interface of the Serial ATA controller complies with PCI Specification Revision 2.2. The chip also
complies with revision 1.0 of the scatter / gather host DMA mechanism of “Programming Interface for Bus Master IDE
Controller”. The VT8237R complies with Serial ATA Specification Revision 1.0 and includes two internal Serial-ATA direct
interfaces (i.e., a two-channel S-ATA PHY is provided on-chip) plus two Parallel-ATA channels (primary and secondary). An
external S-ATA PHY is also supported which is multiplexed on the P-ATA secondary interface. By that mechanism, an external
Serial-ATA PHY can be implemented on the secondary Parallel-ATA interface for support of up to four S-ATA devices total (see
figures below) along with two Parallel-ATA devices (master and slave) on the Parallel-ATA primary channel.
Host
Interface
Transport 1
SRAM
SRAM
Transport 2
Mux
Parallel ATA EIDE Controller
Link 1
PHY1
PHY2
Link 2
SATA 1
SATA 2
SATA Controller
PATA Primary Channel
Slave
Master
PATA Secondary Channel
Figure 2. Block Diagram with 2 Serial–ATA devices