Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -104- Device 17 Function 0 Bus Control Registers
GPIO and Miscellaneous Control
Offset 58 – Miscellaneous Control 0 (40h) ......................RW
7 PCI DMA Pair B
0 Disable (AD5=GPIO25, AC6=GPIO31)default
1 Enable (AD5=PCREQB, AC6=PCGNTB)
6 Internal APIC
0 Disable
(R25=GPIO10,T23=GPIO11,U23=GPI19)
1 Enable...................................................default
(R25=APICD0,T23=APICD1,U23=APICCK)
5 South Bridge Interrupt Cycles Run at 33 MHz
0 Disable ...................................................default
1 Enable
4 Address Decode
0 Subtractive .............................................default
1 Positive
3 RTC High Bank Access
0 Disable access to upper 128 bytes..........default
1 Enable access to upper 128 bytes
2 RTC Rx32 Write Protect
0 Disable (not protected)...........................default
1 Enable (write protected)
1 RTC Rx0D Write Protect
0 Disable (not protected)...........................default
1 Enable (write protected)
0 RTC Rx32 Map to Century Byte
Controls whether RTC Rx32 is mapped to the
century byte.
0 Disable ...................................................default
1 Enable
Offset 59 – Miscellaneous Control 1 (00h)...................... RW
7 ROM Memory Cycles Go To LPC
0 Disable (all memory cycles go to LPC). default
1 Enable (only ROM memory cycles go to LPC)
6 Internal ISA Cycles Arbitrate with Secondary
IDE
0 Disable (Internal ISA cycles do not arbitrate
with secondary IDE).............................. default
1 Enable (all internal ISA cycles arbitrate with
secondary IDE)
5 LPC RTC
0 Disable................................................... default
1 Enable
4 LPC Keyboard
0 Disable (ISA Keyboard) ........................ default
1 Enable (LPC Keyboard)
3 Port 62h / 66h (MCCS#) to LPC
0 Disable................................................... default
1 Enable
2 Port 62h / 66h (MCCS#) Decoding
0 Disable................................................... default
1 Enable
1 A20M# Active
0 Disable (A20M# signal not asserted) .... default
1 Enable (A20M# signal asserted)
0 NMI on PCI Parity Error
0 Disable................................................... default
1 Enable (to generate NMI, Port 61[3] and Port
70[7] must also be set)