Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -3- Product Features
• System Management Bus Interface
− Host interface for processor communications
− Slave interface for external SMBus masters
• Concurrent PCI Bus Controller
−
33 MHz operation
− Supports up to six PCI masters
− Peer concurrency
− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
− Zero wait state PCI master and slave burst transfer rate
− PCI to system memory data streaming up to 132Mbyte/sec (north bridge data transfer via high speed V-Link)
− PCI master snoop ahead and snoop filtering
− Eight DW of CPU to PCI posted write buffers
− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
− Four lines of post write buffers from PCI masters to DRAM
− Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
− Delay transaction from PCI master accessing DRAM
− Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
− Symmetric arbitration between Host/PCI bus for optimized system performance
− Complete steerable PCI interrupts
− PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
• Sophisticated PC2001-Compatible Mobile Power Management
− Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
− ACPI v2.0 and APM v1.2 Compliant
− CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
− PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control
− Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
− Multiple suspend power plane controls and suspend status indicators
− One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
− Normal, doze, sleep, suspend and conserve modes
− Global and local device power control
− System event monitoring with two event classes
− Primary and secondary interrupt differentiation for individual channels
− Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for
system wake-up
− 32 general purpose input ports and 32 output ports
− Multiple internal and external SMI sources for flexible power management models
− Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
− Thermal alarm on external temperature sensing circuit
− I/O pad leakage control
• Plug and Play Controller
− PCI interrupts steerable to any interrupt channel
− Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio
− Microsoft Windows XP
TM
, Windows NT
TM
, Windows 2000
TM
, Windows 98
TM
and plug and play BIOS compliant
• Built-in NAND-tree pin scan test capability
• 0.22um, 2.5V, low power CMOS process
• Single chip 27 x 27 mm, 1.0 mm ball pitch, 539 pin BGA