Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -101- Device 17 Function 0 Bus Control Registers
Miscellaneous Control
Offset 4C - IDE Interrupt Routing (04h) ........................RW
7-6 I/O Recovery Time Select
When Rx40[6] is enabled, this field determines the
I/O recovery time.
00 1 Bus Clock............................................default
01 2 Bus Clock
10 4 Bus Clock
11 8 Bus Clock
5-4 Reserved (do not program) ..................... default = 0
3-2 IDE Secondary Channel IRQ Routing
00 IRQ14
01 IRQ15.....................................................default
10 IRQ10
11 IRQ11
1-0 IDE Primary Channel IRQ Routing
00 IRQ14.....................................................default
01 IRQ15
10 IRQ10
11 IRQ11
Note: When the internal APIC is enabled, internal IRQ
routing to the APIC is fixed as follows:
INTA# => IRQ16
INTB# => IRQ17
INTC# => IRQ18
INTD# => IRQ19
IDE (Native Mode)/SATA IRQ & INTE => IRQ20
USB IRQ (all 5 functions) and INTF => IRQ21
AC’97 / MC’97 IRQ and INTG => IRQ22
LAN IRQ and INTH => IRQ23
Table 9. APIC Fixed IRQ Routing
Offset 4D – Miscelleneous Control (00h).........................RW
7-6 LPC Firmware Burst Length Select
00 Disable burst read...................................default
01 Support 4-byte burst read
10 -reserved-
11 Support 4-byte burst read / write & 16-byte
burst read
5-3 Reserved ........................................ always reads 0
2 Serial IRQs Always Shared in APIC Mode
0 Disable ...................................................default
1 Enable
1 Reserved ........................................ always reads 0
0 LPC TPM Function
0 Disable ...................................................default
1 Enable
Offset 4E - Internal RTC Test Mode .............................. RW
7 RTC High Bank Rx38-3F R/W Protect
0 Disable (allow R/W).............................. default
1 Enable (Protect)
6 RTC Low Bank Rx38-3F R/W Protect
0 Disable (allow R/W).............................. default
1 Enable (Protect)
5 Reserved ........................................always reads 0
4 Last Port 70/74 Written Status
0 Last write was to port 70 ....................... default
1 Last write was to port 74
3 Extra RTC Port 74/75
The RTC is normally accessed though ports 70/74.
This bit controls whether two extra ports (74 / 75)
can be used to access the RTC.
0 Disable................................................... default
1 Enable
2-0 Reserved (Do Not Program) ....................default = 0
Offset 4F – PCI Bus and CPU Interface Control........... RW
7-4 Reserved ........................................always reads 0
3 CPU Reset Source
This bit determines whether CPU Reset (generated
through port 92 or the keyboard) uses INIT or
CPURST.
0 Do not use CPURST as CPU Reset....... default
1 Use INIT as CPU Reset
2 Reserved (Do Not Program) ....................default = 0
1 Reserved ........................................always reads 0
0 Software PCI Reset ......write 1 to generate PCI reset