Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -100- Device 17 Function 0 Bus Control Registers
Offset 44 – PCI PNP Interrupt Routing INTE/F............RW
7-4 PCI INTF# Routing (see PnP IRQ routing Table 11)
3-0 PCI INTE# Routing (see PnP IRQ routing Table 11)
Offset 45 – PCI PNP Interrupt Routing INTG/H ..........RW
7-4 PCI INTH# Routing
(see PnP IRQ routing Table 11)
3-0 PCI INTG# Routing
(see PnP IRQ routing Table 11)
Offset 46 – PCI INTE-F Interrupt Control ....................RW
7-5 Reserved ........................................ always reads 0
4 PCI INT Sharing Control
0 INTE shared with INTA ........................default
INTF shared with INTB
INTG shared with INTC
INTH shared with INTD
1 INTE-INTH routing per Rx44-45
The following bits all default to “level” triggered (0)
3 PCI INTH# Invert (edge) / Non-invert (level) .(1/0)
2 PCI INTG# Invert (edge) / Non-invert (level) .(1/0)
1 PCI INTF# Invert (edge) / Non-invert (level)..(1/0)
0 PCI INTE# Invert (edge) / Non-invert (level)..(1/0)
Note: For routing control of PCI INTA-INTD, see Device
17 Function 0 Rx54-57 and Table 11.
Offset 48 – Read Pass Write Control...............................RW
7 APIC FSB Fixed at Low DW
0 Disable (Address Bit-2 not masked) ......default
1 Enable (force A2 from APIC FSB to low)
Address bit A2 controls whether data is in the lower
(0) or upper (1) doubleword of a quadword sent to
the CPU. When this bit is enabled, A2 is masked
which means it is always 0 to select the lower
doubleword.
6-4 Reserved ........................................ always reads 0
3 AC97 / LPC Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) ...default
1 Enable (internal AC97 and LPC devices are
allowed to perform a read before a preceeding
write)
2 IDE Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) ...default
1 Enable (the internal IDE controller is allowed
to perform a read before a preceeding write)
1 USB Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) ...default
1 Enable (the internal USB controllers are
allowed to perform a read before a preceeding
write)
0 NIC Read Pass Write
0 Disable (a read cannot be performed before a
preceeding write has been completed) ...default
1 Enable (the internal LAN controller is allowed
to perform a read before a preceeding write)
Offset 49 – CCA Control.................................................. RW
7 Reserved ........................................always reads 0
6 South Bridge Internal Master Devices Priority
Higher Than External PCI Master
0 Disable................................................... default
1 Enable
The “CCA” is an internal arbiter that controls the
priority of external PCI masters vs. internal master
devices. Normally priority is the same for internal
and external PCI master devices, but when this bit is
enabled, internal master devices are given higher
priority than external PCI masters (3/4 : 1/4).
5 CCA Clean to Mask Off IRQ
Controls whether interrupt requests are gated until
data is written to memory.
0 Disable................................................... default
1 Enable
4-3 Reserved (Do Not Program) ....................default = 0
2 WSC Mask Off INTR
Controls whether INTR is masked until write snoop
is complete.
0 Disable................................................... default
1 Enable
1-0 Reserved (Do Not Program) ....................default = 0
LPC Firmware Memory Control
Offset 4A – LPC Firmware Memory Control 1 ............. RW
7-1 LPC Firmware Memory Base Address A[23:17]
0 LPC Firmware Memory Programmable IDSEL
0 Disable................................................... default
1 Enable
Offset 4B – LPC Firmware Memory Control 2 ............. RW
7 Reserved ........................................always reads 0
6-4 LPC Firmware Memory Base Address Mask
bit-6 = 1 to mask A19 decoding
bit-5 = 1 to mask A18 decoding
bit-4 = 1 to mask A17 decoding
3-0 LPC Firmware Memory IDSEL Value