Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -95- Device 16 Function 5 USB Direct Device Communications Registers
USB Device Endpoint Controller Operation
Offset 23-20 – Endpoint 0 Status/Control (0040 0000h) WC
This endpoint is a “Control” endpoint with a default maximum
packet size of 64 bytes. See right-hand column for Status /
Control bit descriptions for all 4 endpoints.
Offset 37-24 – Endpoint 0 Transfer Descriptor..............RW
See following pages for “Control Endpoint” transfer descriptor
definition.
Offset 43-40 – Endpoint 1 Status/Control (1200 8000h) RW
This endpoint is a “Bulk In” endpoint with a default maximum
packet size of 512 bytes. See right-hand column for Status /
Control bit descriptions for all 4 endpoints.
Offset 5B-44 – Endpoint 1 Transfer Descriptor .............RW
See following pages for “Bulk In” transfer descriptor
definition.
Offset 63-60 – Endpoint 2 Status/Control (2200 8000h) RW
This endpoint is a “Bulk Out” endpoint with a default
maximum packet size of 512 bytes. See right-hand column for
Status / Control bit descriptions for all 4 endpoints.
Offset 7B-64 – Endpoint 2 Transfer Descriptor .............RW
See following pages for “Bulk Out” transfer descriptor
definition.
Offset 83-80 – Endpoint 3 Status/Control (3008 4000h) RW
This endpoint is an “Interrupt In” endpoint with a default
maximum packet size of 8 bytes. See right-hand column for
Status / Control bit descriptions for all 4 endpoints.
Offset 8B-84 – Endpoint 3 Transfer Descriptor .............RW
See following pages for “Interrupt In” transfer descriptor
definition.
Endpoints 0-3 Status / Control Bit Definitions
31-28 Endpoint ID Number .............................default = 0h
Only the 2 lsbs are writable since only four endpoints
are implemented in this design.
27 Reserved ........................................always reads 0
26-16 Endpoint Max Packet Size. default = max FIFO size
This field specifies the maximum packet size of this
endpoint. The value programmed must not exceed
that defined in the capability registers.
.................................default = 64 bytes for endpoint 0
.......................... default = 512 bytes for endpoints 1-2
...................................default = 8 bytes for endpoint 3
15-14 Endpoint Type ..................................................... RO
00 Control endpoint.......... default for endpoint 0
01 Interrupt endpoint ....... default for endpoint 3
10 Bulk I/O endpoint .. default for endpoints 1-2
11 Isochronous endpoint.... (unused in this design)
13 Reserved ........................................always reads 0
12 Endpoint DMA Engine Active Status................ RO
Set by the endpoint controller if it starts the DMA
engine (including USB & OCI bus traffic), cleared on
DMA process complete. When this bit is 1, software
must not modify the related data buffer. .... default = 0
11 Endpoint Stalled
If this bit is set, the DMA engine will halt
immediately and return a STALL handshake to USB
bus queries. The endpoint controller will also set this
bit if the DMA engine encounters a serious error.
0 Endpoint not stalled............................... default
1 Endpoint stalled
10 Endpoint Transfer Complete ....... Write 1 to Clear
The controller sets this bit when it completes a
transfer if the schedule has its IOC bit set. If
interrupts are enabled, the controller will also
generate an interrupt...................................default = 0
9-3 Reserved ........................................always reads 0
2 Endpoint Light Reset
This bit is cleared by hardware on reset complete.
Software should wait until this bit goes back to 0
before initiating any further operations)
0 No reset ................................................. default
1 Endpoint light reset
1 Endpoint DMA Engine
Software may disable the DMA engine by clearing
this bit to remove the schedule. Software must check
to make sure the DMA active status is zero before
removing or modifying the schedule.
0 Disable................................................... default
1 Enable (activate the DMA engine)
0 Endpoint Run / Stop
Hardware clears this bit if a serious error is detected.
0 Stop (the controller will not respond to any
USB host packets) ................................. default
1 Run (when set, the endpoint controller starts
executing the specified descriptor)