Product specifications

VT8237R Data Sheet
Revision 2.06 December 15, 2004 -93- Device 16 Function 5 USB Direct Device Communications Registers
USB Device Controller Operation
Offset 11-10 – USB Device Command (0010h) ...............RW
15 Device Address Change........................... default = 0
This bit is cleared by hardware when the next SETUP
command is received. When this bit is 1, hardware
will decode both the old address and the newly
changed address. When changing the device address,
this bit must also be set for status phase decoding.
14-8 Device Address..................................... default = 00h
This field specifies the device address. This field is
reset to its default value if a USB bus reset is
received. This field should be programmed by
software after the address setup procedure is
complete.
7-5 Reserved ........................................ always reads 0
4 Device Controller High Speed Support
0 Disable (full speed only) ........................default
1 Enable (high speed supported)
3 Device Force Resume
0 Disable ...................................................default
1 Enable
This bit forces the suspended device port to issue a
resume signal to wakeup the host. Hardware clears
this bit automatically after it is set by software.
Suspend status must be checked before setting this
bit.
2 Automatic Device Mode
0 Manual mode .........................................default
1 Automatic Mode (the device controller
automatically controls the dedicated port for
device operation)
1 Controller Reset
0 Disable ...................................................default
1 Enable (writing a 1 to this bit resets the device
controller; this bit is set to 0 by hardware
when the reset process is complete)
0 Run / Stop
0 Stop .....................................................default
1 Run (setting this bit enables device controller
operations, including host / device negotiation
and endpoint DMA)
Offset 13-12 – USB Device Status (0010h)...................... WC
15-8 Reserved ........................................always reads 0
7 Device Port Resume Detected..........write 1 to clear
This bit indicates whether the controller has detected
bus host resume.
0 No resume detected ............................... default
1 Host resume detected
6 Device Port Bus Suspend Detected .write 1 to clear
This bit indicates whether the controller has detected
bus suspend. If the bus suspend is detected, pullup
resistor status will also be set.
0 No suspend detected.............................. default
1 Bus suspend detected
5 Device Reset ......................................................... RO
This bit is set by the controller if the USB bus reset is
complete.
0 Not emulated ......................................... default
1 Emulated
4 Controller Halted ................................................ RO
This bit is zero whenever the Run / Stop bit is one.
This bit is set if the controller is stopped.
0 Running
1 Halted ................................................... default
3 Controller System Error..................write 1 to clear
The controller sets this bit to one when a serious error
occurs during a system access. If this bit is set, the
controller also clears the “Run/Stop” bit and sets the
“Halted” bit.
0 No error ................................................. default
1 System error
2 Bus Activities Interrupt ...................write 1 to clear
The controller sets this bit when any USB bus
activities interrupt is generated. Bus activities
include bus reset, bus suspend and bus resume.
0 No bus activities interrupt ..................... default
1 Bus activities interrupt generated
1 Reserved ........................................always reads 0
0 Transaction Complete Interrupt.....write 1 to clear
The controller sets this bit when a transaction is
completed. Software must clear the interrupts from
all endpoints first before clearing this bit.
0 No interrupt ........................................... default
1 Interrupt generated