Data Sheet VT8237R South Bridge Revision 2.06 December 15, 2004 VIA TECHNOLOGIES, INC.
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VT8237R Data Sheet REVISION HISTORY Document Release 1.07 Date 10/9/03 1.08 1.09 1.1 10/9/03 10/16/03 10/23/03 1.11 1.20 11/5/03 2/11/04 1.21 1.22 2/16/04 2/25/04 1.23 3/11/04 1.24 3/31/04 1.25 4/26/04 1.26 1.27 1.28 5/10/04 5/11/04 6/16/04 1.29 7/7/04 1.3 9/6/04 1.31 9/22/04 2.0 2.01 9/22/04 10/13/04 2.02 2.03 2.04 2.05 2.
VT8237R Data Sheet TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES .........................................................................................
VT8237R Data Sheet SATA I/O Registers .............................................................................................................................................................................. 61 Device 15 Function 1 Registers - Enhanced IDE Controller............................................................................................. 62 PCI Configuration Space Header................................................................................................................
VT8237R Data Sheet FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 164 POWER MANAGEMENT .............................................................................................................................................................. 164 Power Management Subsystem Overview ........................................................................................................
VT8237R Data Sheet LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. PC SYSTEM CONFIGURATION USING THE VT8237R...................................................................................... 4 BLOCK DIAGRAM WITH 2 SERIAL–ATA DEVICES......................................................................................... 5 BLOCK DIAGRAM WITH 4 SERIAL–ATA DEVICES.........................................................................................
VT8237R Data Sheet LIST OF TABLES TABLE 1. PIN LIST (NUMERICAL ORDER) ............................................................................................................................. 8 TABLE 2. PIN LIST (ALPHABETICAL ORDER) ...................................................................................................................... 9 TABLE 3. MEMORY MAPPED REGISTERS ........................................................................................................................
VT8237R Data Sheet VT8237R “ULTRA V-LINK” SERIAL ATA SOUTH BRIDGE 16-BIT V-LINK FOR HIGH BANDWIDTH NORTH BRIDGE DATA TRANSFER, DUAL CHANNEL SERIAL ATA / RAID CONTROLLER, ULTRADMA-133/100/66/33 MASTER MODE EIDE CONTROLLER, INTEGRATED FAST ETHERNET AND EIGHT PORT USB 2.
VT8237R Data Sheet • UltraDMA-133 / 100 / 66 / 33 Master Mode EIDE (Parallel ATA) Controller − Dual channel master mode hard disk controller supporting four Enhanced IDE devices − Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface − Increased reliability using UltraDMA-133/100/66 transfer protocols − Thirty-two levels (doublewords) of prefetch and write buffers − Dual DMA engine for concurrent dual channel operation − Bus master programming interface
VT8237R Data Sheet • System Management Bus Interface − Host interface for processor communications − Slave interface for external SMBus masters • Concurrent PCI Bus Controller − 33 MHz operation − Supports up to six PCI masters − Peer concurrency − Concurrent multiple PCI master transactions; i.e.
VT8237R Data Sheet OVERVIEW The VT8237R South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft PC2001-compliant PCI/LPC system. The VT8237R includes standard intelligent peripheral controllers: a) Serial ATA dual channel controller with RAID capability.
VT8237R Data Sheet The VT8237R also enhances the functionality of standard integrated peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT8237R supports delayed transactions and remote power management so that slower internal ISA peripherals do not block the traffic of the PCI bus.
VT8237R Data Sheet Link 1 PHY1 Link 2 PHY2 SATA Devices 1 Transport 1 SRAM 2 Mux Host Interface Link 3 Transport 2 Link 4 SRAM Serial-ATA LITE Interface SATA Lite PHY 3 4 SATA Controller PATA Primary Channel Parallel ATA EIDE Controller Master Slave Figure 3. Block Diagram with 4 Serial–ATA devices Revision 2.
VT8237R Data Sheet PINOUTS Key 1 Figure 4.
VT8237R Data Sheet Table 1.
VT8237R Data Sheet Table 2.
VT8237R Data Sheet PIN DESCRIPTIONS V-Link Pin Descriptions V-Link Interface Signal Name Pin # I/O Signal Description VD[15:0] (see pin list) IO VPAR F24 IO VBE# VCLK UPCMD DNCMD UPSTB UPSTB# DNSTB DNSTB# G24 L22 K23 K25 J26 J24 H26 H24 IO I O I O O I I Data Bus. All bits 15-0 are implemented for use with VIA north bridge chips which support this capability (if not, only bits 7-0 are used).
VT8237R Data Sheet CPU, APIC and CPU Control Pin Descriptions CPU Interface Signal Name Pin # I/O Signal Description OD A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20). U24 I Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the FERR# CPU. Internally generates interrupt 13 if active.
VT8237R Data Sheet PCI Bus Pin Descriptions PCI Bus Interface Signal Name AD[31:0] CBE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# SERR# PERR# PAR INTA# INTB# INTC# INTD# INTE# / GPI12, / GPO12, INTF# / GPI13, / GPO13, INTG# / GPI14, / GPO14, INTH# / GPI15, / GPO15 REQ5# / GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5# / GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0# PCIRST# PCICLK PCKRUN# Pin # I/O Signal Description (see pin IO Address / Data Bus. Multiplexed address and data.
VT8237R Data Sheet MII, Serial EEPROM and Low Pin Count Pin Descriptions LAN Controller - Media Independent Interface (MII) Signal Name Pin # I/O MCOL MCRS B11 A11 I I MDCK A7 O MDIO B7 IO C9 C7, A8, B8, C8 I I MRXDV MRXERR D8 D10 I I MTXCLK C10 I MTXD[3-0] A9, B9, B10, A10 O MTXENA C11 O PHYRST# MIIVCC D7 D9, E9 - 11 O Power MIIVCC25 LANVCC LANGND D12, E12 E7 E6 Power Power Power MRXCLK MRXD[3-0] PU Signal Description PD MII Collision Detect. From the external PHY.
VT8237R Data Sheet USB, SMB Pin Descriptions Universal Serial Bus 2.
VT8237R Data Sheet Enhanced IDE Interface Pin Descriptions UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface Signal Name Pin # I/O Signal Description PDRDY / PDDMARDY / PDSTROBE Y22 I SDRDY / SDDMARDY / SDSTROBE AF17 I PDIOR# / PHDMARDY / PHSTROBE W26 O SDIOR# / SHDMARDY / SHSTROBE AF23 O PDIOW# / PSTOP Y25 O SDIOW# / SSTOP AE23 O PDDRQ SDDRQ PDDACK# / strap SDDACK# IRQ14 IRQ15 Y23 AD17 V24 AD23 AD24 AE26 I I O O I I Revision 2.
VT8237R Data Sheet UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (continued) Signal Name Pin # PDCS1# / strap V22 O PDCS3# / strap V23 O SDCS1# AF25 O SDCS3# AF26 O W24, V25, W23 O AE24, AC22, AF24 (see pin list) (see pin list) O PDA[2-0] / strap SDA[2-0] PDD[15-0] SDD[15-0] I/O Signal Description IO IO Primary Master Chip Select. This signal corresponds to CS1FX# on the primary IDE connector. Primary Slave Chip Select.
VT8237R Data Sheet AC’97 Audio and Modem Pin Descriptions AC97 Audio / Modem Interface Signal Name Pin # I/O Signal Description T3 O AC97 Reset. ACRST# T1 I AC97 Bit Clock. ACBTCK ACSYNC / strap T2 O AC97 Sync. ACSDOUT / strap U2 O AC97 Serial Data Out. ACSDIN0 (VSUS33)† U3 I AC97 Serial Data In 0. ACSDIN1 (VSUS33)† V2 I AC97 Serial Data In 1. ACSDIN2 / GPIO20 / PCS0# U1 I AC97 Serial Data In 2. RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1 ACSDIN3 / GPIO21 / PCS1# / SLPBTN# V3 I AC97 Serial Data In 3.
VT8237R Data Sheet Internal Keyboard Controller and Speaker Pin Descriptions Internal Keyboard Controller Signal Name Pin # I/O PU W1 IO PU Signal Description Mouse Clock. From internal mouse controller. Dev17 Fun0 Rx51[2]=1. W2 IO PU Mouse Data. From internal mouse controller. MSDT Dev17 Fun 0 Rx51[2]=1. KBCK / KA20G W3 IO PU MultiFunction Pin (Internal keyboard controller enabled by Dev17 Fun 0 Rx51[0]) Rx51[0]=1 Keyboard Clock. From internal keyboard controller Rx51[0]=0 Gate A20.
VT8237R Data Sheet Programming Chip Selects Pin Descriptions Programmable Chip Selects Signal Name Pin # PCS0# / GPIO20 / ACSDIN2 PCS1# / GPIO21 / ACSDIN3 / SLPBTN# U1 V3 I/O Signal Description O O Programmable Chip Select 0. RxE4[6]=1, E5[1]=1 Programmable Chip Select 1. RxE4[6]=1, E5[2]=1 General Purpose Inputs Pin Descriptions General Purpose Inputs Signal Name Pin # General Purpose Input 0. Status on PMIO Rx20[0] General Purpose Input 1. Status on PMIO Rx20[1] General Purpose Input 2.
VT8237R Data Sheet General Purpose Outputs Pin Descriptions General Purpose Outputs Signal Name Pin # I/O Signal Description GPO0 (VSUS33) GPO1 (VSUS33) GPO2 / SUSA# (VSUS33) GPO3 / SUSST1# (VSUS33) GPO4 / SUSCLK (VSUS33) GPO5 / CPUSTP# GPO6 / PCISTP# GPO7 / GNT5# GPO8 / GPI8 / VGATE GPO9 / UDPWREN GPO10 / GPI10 / APICD0 GPO11 / GPI11 / APICD1 GPO12 / GPI12 / INTE# GPO13 / GPI13 / INTF# GPO14 / GPI14 / INTG# GPO15 / GPI15 / INTH# GPO20 / GPI20 / ACSDIN2 / PCS0# GPO21 / GPI21 / ACSDIN3 / PCS1# /SLPBTN# G
VT8237R Data Sheet Power Management and Event Pin Descriptions Power Management and Event Detection Signal Name Pin # I/O Signal Description PWRBTN# AD2 SLPBTN# / GPIO21 / ACSDIN3 / PCS1# RSMRST# EXTSMI# / GPI2 PME# SMBALRT# LID# / GPI4 INTRUDER# / GPI16 THRM# / GPI18 / AOLGPI RING# / GPI3 BATLOW# / GPI5 CPUSTP# / GPO5 PCISTP# / GPO6 / strap SUSA# / GPO2 SUSB# SUSC# SUSST1# / GPO3 SUSCLK CPUMISS / GPI17 AOLGPI / GPI18 / THRM# Power Button.
VT8237R Data Sheet Clocks, Resets, Power Status, Power and Ground Pin Descriptions Resets, Clocks, and Power Status Signal Name Pin # I/O Signal Description PWRGD AC5 I PWROK# PCIRST# AF1 R1 O O OSC RTCX1 AB8 AE4 I I RTCX2 TEST TPO AF3 AE9 AF9 O I O Power Good. Connected to the Power Good signal on the Power Supply. Internal logic powered by VBAT. Power OK. Internal logic powered by VSUS33. PCI Reset. Active low reset signal for the PCI bus.
VT8237R Data Sheet Strap Pin Descriptions Strap Pins (External pullup / pulldown straps are required to select “H” / “L”) Strap Pins for VT8237R Configuration Signal SPKR Pin# AF8 ACSDOUT U2 EEDI A12 Function CPU Frequency Strapping Auto Reboot Eliminate External LAN EEPROM ACSYNC T2 LPC FWH Command PDCS1# V22 SATA Master / Slave Mode PDDACK# V24 PCISTP# / GPO6 AD6 External SATA PHY Reserved PDCS3# V23 NB Configuration PDA2 W24 NB Configuration PDA1 V25 NB Configuration GPIOD / P
VT8237R Data Sheet REGISTERS Register Overview Table 5. System I/O Map The following tables summarize the configuration and I/O registers of the VT8237R. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits).
VT8237R Data Sheet Table 6.
VT8237R Data Sheet Keyboard / Mouse Wakeup Registers (I/O Space) Memory Mapped Registers – IOAPIC Default Acc Port KB / Mouse Wakeup Registers 002E Keyboard / Mouse Wakeup Index † 00 RW 002F Keyboard / Mouse Wakeup Data † 00 RW † Keyboard / Mouse Wakeup registers (index values E0-EF defined below) are accessible if Function 0 PCI Configuration register Rx51[1] = 1.
VT8237R Data Sheet Device 15 Function 0 Registers – SATA Controller Configuration Space SATA Header Registers Default Offset Configuration Space Header 1-0 Vendor ID 1106 3-2 Device ID 3149 5-4 Command 0000 7-6 Status 0290 8 Revision ID 80 9 Programming Interface 8F A Sub Class Code (RAID Controller) 04 B Base Class Code (Mass Storage) 01 C Cache Line Size 00 D Latency Timer 20 E Header Type (MultiFunction Device) 80 F -reserved00 13-10 Base Address – Pri Data / Command 000001F1 17-14 Base Address – Pri Con
VT8237R Data Sheet Configuration Space SATA-Specific Registers (continued) Offset Transport Status Registers Default Acc 78 Primary Channel Transport Status I 01 RO 79 Primary Channel Transport Status II 00 RO 7A Sec Channel Transport Status I 01 RO 7B Sec Channel Transport Status II 00 RO Offset 7C 7D 7E-7F PHY Status Registers Internal PHY Status External PHY Status -reserved- Offset 80 81 82-87 8B-88 8F-8C Channel Control Registers Pri Channel Device Mode Status Sec Channel Device Mode Status -reserve
VT8237R Data Sheet Device 15 Function 1 Registers – PATA (IDE) Controller Configuration Space IDE Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status 8 Revision ID 9 Programming Interface A Sub Class Code (IDE Controller) B Base Class Code (Mass Storage) C-F -reserved13-10 Base Address – Pri Data / Command 17-14 Base Address – Pri Control / Status 1B-18 Base Address – Sec Data / Command 1F-1C Base Address – Sec Control / Status 23-20 Base Address – Bus Maste
VT8237R Data Sheet Device 16 Function 0 Registers – USB 1.
VT8237R Data Sheet Device 16 Function 1 Registers – USB 1.
VT8237R Data Sheet Device 16 Function 2 Registers – USB 1.
VT8237R Data Sheet Device 16 Function 3 Registers – USB 1.
VT8237R Data Sheet Device 16 Function 4 Registers – USB 2.
VT8237R Data Sheet Device 16 Func 5 Registers – USB Device Communications Configuration Space USB Device Comm Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E-F 13-10 14-2B 2D-2C 2F-2E 30-33 34 35-3B 3C 3D 3E-3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code Cache Line Size Latency Timer -reservedUDCI Mem Mapped I/O Base Addr -reservedSub Vendor ID Sub Device ID -reservedPower Management Capabilities -reservedInterrupt Lin
VT8237R Data Sheet Device 17 Function 0 Registers – Bus Control & Power Management Configuration Space Bus Control & PM Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-27 28-2B 2D-2C 2F-2E 30-33 34-3B 3C 3D 3E 3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built In Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) Sub Ve
VT8237R Data Sheet Configuration Space Power Management Registers Offset 80 81 82 83 85-84 87-86 8B-88 8C 8D 8E-8F 93-90 94 95 96 97 98 99 9A 9B-A0 A1 A2 A3 A4-BF C3-C0 C7-C4 C8-CF Power Management General Configuration 0 General Configuration 1 ACPI Interrupt Select -reservedPrimary Interrupt Channel Secondary Interrupt Channel Power Mgmt I/O Base (256 Bytes) Host Bus Power Mgmt Control Throttle / Clock Stop Control -reservedGP Timer Control Power Well Control Miscellaneous Control Power On / Reset Contro
VT8237R Data Sheet I/O Space Power Management Registers I/O Space System Management Bus Registers Offset 1-0 3-2 5-4 6-7 B-8 C-F Basic Control / Status Registers Power Management Status Power Management Enable Power Management Control -reservedPower Management Timer -reserved- Default 0000 0000 0000 00 0000 0000 00 Acc WC RW RW — RW — Offset 13-10 14 15 16-1F Processor Registers Processor and PCI Bus Control Processor LVL2 Processor LVL3 -reserved- Default 0000 0000 00 00 00 Acc RW RO RO — Offset
VT8237R Data Sheet Device 17 Function 5 & 6 Registers – AC/MC97 Codecs Function 5 Configuration Space AC97 Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C-F 13-10 17-14 1B-18 1F-1C 23-20 27-24 28-29 2F-2C 33-30 34 35-3B 3C 3D 3E 3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code -reservedBase Address 0 - SGD Control/Status Base Address 1 (reserved) Base Address 2 (reserved) Base Address 3 (reserved) Base Address 4 (reserved) B
VT8237R Data Sheet Function 5 I/O Base 0 Registers – AC97 Audio S/G DMA 7B-78 7F-7C AC97 SGD I/O Registers SGD Channel x Status SGD Channel x Control SGD Channel x Left Volume SGD Channel x Right Volume SGD Channel x Table Pointer Base SGD Channel x Current Address Stop Index / Data Type / Sample Rate SGD Channel x Current Count SGD 3D Channel Status SGD 3D Channel Control SGD 3D Channel Format SGD 3D Channel Scratch SGD 3D Channel Table Pointer Base SGD 3D Channel Current Address SGD 3D Channel Slot Sele
VT8237R Data Sheet Device 18 Function 0 Registers - LAN Configuration Space LAN Header Registers Default Offset Configuration Space Header 1-0 Vendor ID 1106 3-2 Device ID 3065 5-4 Command 0000 7-6 Status 0470 8 Revision ID 40 9 Programming Interface 00 A Sub Class Code 00 B Base Class Code 00 C Cache Line Size 00 D Latency Timer 00 E Header Type 00 F BIST 00 13-10 I/O Base Address 0000 0000 17-14 Memory Base Address 0000 0000 18-27 -reserved00 2B-28 Card Bus CIS Pointer 0000 0000 2C-2F -reserved00 33-30 Ex
VT8237R Data Sheet I/O Space LAN Registers Offset Power Management 5-0 Ethernet Address 6 Receive Control 7 Transmit Control 8 Command 0 9 Command 1 A-B -reservedC Interrupt Status 0 D Interrupt Status 1 E Interrupt Mask 0 F Interrupt Mask 1 17-10 Multicast Address 1B-18 Receive Address 1F-1C Transmit Address 23-20 Receive Status 27-24 Receive Data Buffer Control 2B-28 Receive Data Buffer Start Address 2F-2C Receive Data Buffer Branch Address 30-3F -reserved43-40 Transmit Status 47-44 Transmit Data Buffer C
VT8237R Data Sheet Register Descriptions Port 61 - Misc Functions & Speaker Control................. RW 7 SERR# Status .......................................................RO 0 SERR# has not been asserted ................ default 1 SERR# was asserted by a PCI agent Note: This bit is set when the PCI bus SERR# signal is asserted. Once set, this bit may be cleared by setting bit-2 of this register. Bit-2 should be cleared to enable recording of the next SERR# (i.e.
VT8237R Data Sheet Port 60 - Keyboard Controller Input Buffer.................. WO Only write to port 60h if port 64h bit-1 = 0 (1=full). Keyboard Controller I/O Registers The keyboard controller handles the keyboard and mouse interfaces. Two ports are used: port 60 and port 64. Reads from port 64 return a status byte. Writes to port 64h are command codes (see command code list following the register descriptions). Input and output data is transferred via port 60.
VT8237R Data Sheet Port 64 - Keyboard / Mouse Command ..........................WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT8237R are listed in the table below. Table 7.
VT8237R Data Sheet DMA Controller I/O Registers Ports 80-8F - DMA Page Registers There are eight DMA Page Registers, one for each DMA channel. These registers provide bits 16-23 of the 24-bit address for each DMA channel (bits 0-15 are stored in registers in the Master and Slave DMA Controllers). They are located at the following I/O Port addresses: Ports 00-0F - Master DMA Controller Channels 0-3 of the Master DMA Controller control System DMA Channels 0-3.
VT8237R Data Sheet Interrupt Controller Shadow Registers Interrupt Controller I/O Registers The following shadow registers are enabled by setting function 0 Rx47[4]. If the shadow registers are enabled, they are read back at the indicated I/O port instead of the standard interrupt controller registers (writes are unchanged). Ports 20-21 - Master Interrupt Controller The Master Interrupt Controller controls system interrupt channels 0-7. Two registers control the Master Interrupt Controller.
VT8237R Data Sheet Offset 00 01 02 03 04 CMOS / RTC I/O Registers Port 70 - CMOS Address..................................................RW 7 NMI Disable ........................................................ RW 0 Enable NMI Generation. NMI is asserted on encountering SERR# on the PCI bus. 1 Disable NMI Generation ........................default 6-0 CMOS Address (lower 128 bytes) ...................... RW 05 Port 71 - CMOS Data........................................................
VT8237R Data Sheet Keyboard / Mouse Wakeup Index / Data Registers Index E1 – Keyboard Wakeup Scan Code Set 0 (F0h).. RW 7-0 Keyboard Wakeup First Scan Code .........def = F0h Index E2 – Keyboard Wakeup Scan Code Set 1 (00h) .. RW 7-0 Keyboard Wakeup Second Scan Code .....def = 00h Index E3 – Keyboard Wakeup Scan Code Set 2 (00h) .. RW 7-0 Keyboard Wakeup Third Scan Code .......def = 00h Index E4 – Keyboard Wakeup Scan Code Set 3 (00h) .. RW 7-0 Keyboard Wakeup Fourth Scan Code .....
VT8237R Data Sheet Memory Mapped I/O APIC Registers Indexed I/O APIC Registers Memory Address FEC00000 – APIC Index....................RW 7-0 APIC Index .......................................... default = 00h 8-bit pointer to APIC registers. Offset 0 – APIC Identification (0000 0000h) .................. RW 31-28 Reserved ........................................always reads 0 27-24 APIC Identification.................................. default = 0 Software must program this value before using the APIC.
VT8237R Data Sheet Format for Each I/O Redirection Table Entry: Offset 3F-10 – I/O Redirection Table This table contains 24 registers, with one dedicated table entry for each of the 24 APIC interrupt signals. Each 64-bit register consists of two 32-bit values at consecutive index locations, with the low 32 bits at the even index and the upper 32 bits at the odd index. The default value for all registers is xxx1 xxxx xxxx xxxxh. Physical Mode (bit-11=0) 63-60 Reserved ......................................
VT8237R Data Sheet Configuration Space I/O Configuration space accesses for all functions use PCI configuration mechanism 1 (see PCI specification revision 2.2 for more details). The ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged. There are 8 “functions” implemented in the VT8237R (see Table 5 on page 24). The following sections describe the registers and register bits of these functions. Port CFB-CF8 - Configuration Address .........................
VT8237R Data Sheet Offset 9 - Programming Interface (8Fh)......................... RW 7 Master Capability................... fixed at 1 (Supported) 6-4 Reserved ........................................always reads 0 3 Programmable Indicator - Secondary...... fixed at 1 Supports both modes (may be set to either mode by writing Rx42[6]) 2 Channel Operating Mode - Secondary 0 Compatibility Mode 1 Native Mode ......................................... default 1 Programmable Indicator - Primary .........
VT8237R Data Sheet Offset 2D-2C – Sub Vendor ID (1106h)........................... RO Offset 13-10 - Pri Data / Command Base Address .........RW Specifies an 8 byte I/O address space. Offset 2F-2E – Sub Device ID (3149h) ............................. RO 31-16 Reserved ..........................................always read 0 15-3 Port Address....................................... default=01F0h 2-0 Fixed at 001b .....................................................
VT8237R Data Sheet SATA-Controller-Specific Configuration Registers Offset 42 –Native Mode Enable (F1h)............................. RW 7 Primary Channel I/O Native Mode 0 Disable 1 Enable................................................... default 6 Secondary Channel I/O Native Mode 0 Disable 1 Enable................................................... default 5 Primary Channel Interrupt Native Mode Enable 0 Disable 1 Enable...................................................
VT8237R Data Sheet Offset 46 – Miscellaneous Control III (00h) ................... RW 7-3 Reserved..............................................always reads 0 5 IRQ Asserted When Device Is Hot-Plugged 0 Disable................................................... default 1 Enable 4 Reserved (Do Not Program) .................... default = 0 3 Reserved..............................................always reads 0 2 PLL Reset 0 Disable...................................................
VT8237R Data Sheet Offset 4A – SATA External PHY Pad Ctrl I (10h)........ RW 7 VCOMP Internal Latch Control........... RO, def = 0 6-5 VCOMP Output Status (valid only when Bit[4] is 0) ....................................................... RO, def = 0 4 Adjust VCOMP Manually 0 Disable 1 Enable................................................... default 3 SATA Strobe Pad VCOMP Control 1..........def = 0 2 SATA Strobe Pad VCOMP Control 0..........def = 0 1 SATA Data Pad VCOMP Control 1 .............
VT8237R Data Sheet SATA Transport Control Registers SATA Link Control Registers Offset 50 – Software Ctrl Power Mode Request (00h)...RW 7 External PHY Port2 SLUMBER Request ... def = 0 6 External PHY Port2 PARTIAL Request ..... def = 0 5 External PHY Port1 SLUMBER Request ... def = 0 4 External PHY Port1 PARTIAL Request ..... def = 0 3 Internal PHY Port2 SLUMBER Request .... def = 0 2 Internal PHY Port2 PARTIAL Request...... def = 0 1 Internal PHY Port1 SLUMBER Request ....
VT8237R Data Sheet SATA PHY Control Registers Transport Status Registers Offset 5A – Internal SATA PHY Control (10h) .............RW 7 Reserved ......................................................... def = 0 6 Bypass Oscillator ........................................... def = 0 5 OSC Latch up Test Control .......................... def = 0 4 OOB Signal Select 0 AFE 1 Digital ...................................................default 3 Reserved .........................................................
VT8237R Data Sheet PHY Status Registers Power Management Control Registers Offset 7C – Internal PHY Status ......................................RO 7-6 Reserved ................................................... default = 0 5 Port2 Auto Check Error Report............. default = 0 4 Port2 Squelch Detector Output 3-2 Reserved ................................................... default = 0 1 Port1 Auto Check Error Report.............
VT8237R Data Sheet SATA I/O Registers The base address for access of these registers is specified in Rx27-24. Offset B-8 – SATA Control (00000310h) ......................... RO 31-12 Reserved..............................................always reads 0 11-18 IPM Represents the enabled interface power management states that can be invoked via SATA interface power management capabilities.
VT8237R Data Sheet Device 15 Function 1 Registers - Enhanced IDE Controller This Enhanced IDE (Parallel ATA) controller interface is fully compatible with the SFF 8038i v.1.0 specification. There are two sets of software accessible registers -- PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the device 15 function 1 PCI configuration space of the VT8237R. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification.
VT8237R Data Sheet Offset 13-10 - Pri Data / Command Base Address .........RW Specifies an 8 byte I/O address space. Offset 2D-2C – Sub Vendor ID (0000h)........................... RO The readback value may be changed by writing to RxD5-D4. 31-16 Reserved ..........................................always read 0 15-3 Port Address....................................... default=01F0h 2-0 Fixed at 001b ..................................................... fixed Offset 2F-2E – Sub Device ID (0000h) ...........
VT8237R Data Sheet IDE-Controller-Specific Configuration Registers Offset 40 - Chip Enable (00h)...........................................RW 7-2 Reserved ........................................ always reads 0 1 Primary Channel 0 Disable ...................................................default 1 Enable 0 Secondary Channel 0 Disable ...................................................default 1 Enable Offset 41 - IDE Configuration I (00h) .............................
VT8237R Data Sheet Offset 44 - Miscellaneous Control 1 (08h) .......................RW 7-5 Reserved ........................................ always reads 0 4 PIO Read Pre-Fetch Byte Counter Determines whether the amount of data prefetched under PIO read is limited. 0 Disable (no limit) ...................................default 1 Enable. The maximum number of bytes that can be prefetched is determined by Rx6160[11:0] for the primary channel and Rx6968[11:0] for the secondary channel.
VT8237R Data Sheet Offset 4B-48 - Drive Timing Control (A8A8A8A8h)......RW The following fields define the Active Pulse Width and Recovery Time for the IDE DIOR# and DIOW# signals when accessing the data ports (1F0 and 170): One Completed Cycle DIOR# / DIOW# Active Time 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0 Recovery Time Primary Drive 0 Active Pulse Width...... def=1010b Primary Drive 0 Recovery Time............. def=1000b Primary Drive 1 Active Pulse Width......
VT8237R Data Sheet Offset 54 – UltraDMA FIFO Control (04h) ....................RW 7 Reserved ........................................ always reads 0 6 Lower ISA Request Priority When Write Device Packet Command is Issued The IDE secondary channel shares a bus internally with the ISA interface. When this bit is enabled, the IDE secondary channel is given higher priority over ISA, which results in better performance. 0 Disable ...................................................
VT8237R Data Sheet Offset 70 – Primary IDE Status ........................................RO 7 Interrupt Status ...................................................RO 1 Primary channel interrupt request pending 6 Prefetch Buffer Status .........................................RO 1 PIO Prefetch transaction in progress 5 Post Write Buffer Status .....................................RO 1 PIO Post Write transaction in progress 4 DMA Read Prefetch Status.................................
VT8237R Data Sheet Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 0 Registers - USB 1.1 UHCI Ports 0-1 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
VT8237R Data Sheet USB 1.1-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h) ...................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.1, when this occurs in the interval just before an EOP, the receiver will accept the packet.
VT8237R Data Sheet Offset 49 - Miscellaneous Control 6 (03h) ...................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) .................... default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ............................................. default 0 UHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ......................
VT8237R Data Sheet USB 1.1 Ports 0-1 I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control Revision 2.
VT8237R Data Sheet Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 1 Registers - USB 1.1 UHCI Ports 2-3 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
VT8237R Data Sheet USB 1.1-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h) ...................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.1, when this occurs in the interval just before an EOP, the receiver will accept the packet.
VT8237R Data Sheet Offset 49 - Miscellaneous Control 6 (03h) ...................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) .................... default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ............................................. default 0 UHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ......................
VT8237R Data Sheet USB 1.1 Ports 2-3 I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 2 Status / Control I/O Offset 13-12 - Port 3 Status / Control Revision 2.
VT8237R Data Sheet Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 2 Registers - USB 1.1 UHCI Ports 4-5 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
VT8237R Data Sheet USB 1.1-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h) ...................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.1, when this occurs in the interval just before an EOP, the receiver will accept the packet.
VT8237R Data Sheet Offset 49 - Miscellaneous Control 6 (03h) ...................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) .................... default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ............................................. default 0 UHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ......................
VT8237R Data Sheet USB 1.1 Ports 4-5 I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 4 Status / Control I/O Offset 13-12 - Port 5 Status / Control Revision 2.
VT8237R Data Sheet Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Device 16 Function 3 Registers - USB 1.1 UHCI Ports 6-7 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
VT8237R Data Sheet USB 1.1-Specific Configuration Registers Offset 41 - Miscellaneous Control 2 (10h) ...................... RW 7 USB 1.1 Improvement for EOP This bit controls whether USB Specification 1.1 or 1.0 is followed when a stuffing error occurs before an EOP (End-Of-Packet). A stuffing error results when the receiver sees seven consecutive ones in a packet. Under USB specification 1.1, when this occurs in the interval just before an EOP, the receiver will accept the packet.
VT8237R Data Sheet Offset 49 - Miscellaneous Control 6 (03h) ...................... RW 7-6 Reserved ........................................always reads 0 5-4 Reserved (Do Not Program) .................... default = 0 3-2 Reserved ........................................always reads 0 1 EHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ............................................. default 0 UHCI Supports PME Assertion in D3 Cold State 0 Not Supported 1 Supported ......................
VT8237R Data Sheet USB 1.1 Ports 6-7 I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 6 Status / Control I/O Offset 13-12 - Port 7 Status / Control Revision 2.
VT8237R Data Sheet Device 16 Function 4 Registers - USB 2.0 EHCI Offset 9 - Programming Interface (20h) .......................... RO Offset A - Sub Class Code (03h=USB Controller) .......... RO Offset B - Base Class Code (0Ch=Serial Bus Controller)RO This Enhanced Serial Bus host controller interface is fully compatible with EHCI specification v1.0. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers.
VT8237R Data Sheet USB 2.0-Specific Configuration Registers Offset 5C - PHY Control (53h)........................................ RW 7 DPLL Zero Phase Start Select 0 ZPS takes 8-bit times to start................ default 1 ZPS takes 4-bit times to start 6-4 Delay DPLL Input Data Control .... default = 101b† 3-2 DPLL Track Speed Select.................... default = 00b 1-0 DPLL Lock Speed Select .....................
VT8237R Data Sheet EHCI USB 2.0 I/O Registers These registers are compliant with the EHCI v1.0 standard. Refer to the EHCI v1.0 specification for further details. EHCI Capabilities I/O Offset 0 - Capability Register Length (10h) I/O Offset 3-2 - Interface Version Number (0100h) ......RO† I/O Offset 7-4 – Structure Parameters (0000 3206h) ...RO† I/O Offset B-8 – Capability Parameters (0000 6872h) .RO† † RW if Rx42[4] = 1.
VT8237R Data Sheet Device 16 Function 5 Registers - USB Direct Device Communications The registers in this function control USB direct device communications. There are two sets of software accessible registers: PCI Configuration registers and Memory Mapped I/O registers. The PCI configuration registers are located in the Device 16 Function 5 PCI configuration space of the VT8237R.
VT8237R Data Sheet USB-Device-Communications-Specific Registers USB Device Communications Control Offset 40 - Miscellaneous Control 1 (00h) .......................RW 7-2 Reserved ........................................ always reads 0 1 DMA Options 0 16 DW burst access................................default 1 8 DW burst access 0 Reserved ........................................ always reads 0 Offset 41 - Miscellaneous Control 2 (00h) .......................RW 7-1 Reserved ...................................
VT8237R Data Sheet USB Device Communications MAC Control USB Device Communications PHY Control Offset 4A – MAC Receiver Enable Delay (00h)..............RW 7-0 MAC Receiver Enable Delay Parameter . def = 00h Offset 58 – PHY Control 1 (00h) ..................................... RW 7 Test UTM Elastic Buffer Error Control 0 Disable................................................... default 1 Enable 6 Reserved ........................................
VT8237R Data Sheet USB Device Communications SRAM Control USB Device Communications Power Management Control Offset 71-70 – SRAM Direct Access Address (0000h)....RW 15-9 Reserved ........................................ always reads 0 8-0 SRAM Direct Access Address..................... def=00h The valid address range for SRAM 0 is 0 to 011h. The valid address range for SRAM 1 is 0 to 100h The valid address range for SRAM 2 is 0 to 100h Offset 83-80 – PM Capability ........................................
VT8237R Data Sheet USB Device Controller Interface (UDCI) Memory Mapped I/O Registers USB Communications Capability USB Shadow Registers Offset 0 – Capability Register Length (10h) ....................RO 7-0 Capability Register Length ..........always reads 10h Offset F-C – EHCI Port 0 Shadow................................... RO This register shadows the EHCI Port 0 Status register. Offset 1 – Interface Version (10h).....................................RO 7-0 Interface Version Number ...........
VT8237R Data Sheet USB Device Controller Operation Offset 11-10 – USB Device Command (0010h) ...............RW 15 Device Address Change ........................... default = 0 This bit is cleared by hardware when the next SETUP command is received. When this bit is 1, hardware will decode both the old address and the newly changed address. When changing the device address, this bit must also be set for status phase decoding. 14-8 Device Address .....................................
VT8237R Data Sheet Offset 15-14 – USB Device Interrupt Enable (0000h) ....RW 15-4 Reserved ........................................ always reads 0 3 Controller System Error Interrupt Enable 0 Disable ...................................................default 1 Enable (the controller will generate an interrupt if a system error occurs) 2 Bus Activities Interrupt Enable 0 Disable ...................................................
VT8237R Data Sheet USB Device Endpoint Controller Operation Offset 23-20 – Endpoint 0 Status/Control (0040 0000h) WC This endpoint is a “Control” endpoint with a default maximum packet size of 64 bytes. See right-hand column for Status / Control bit descriptions for all 4 endpoints. Offset 37-24 – Endpoint 0 Transfer Descriptor ..............RW See following pages for “Control Endpoint” transfer descriptor definition.
VT8237R Data Sheet Endpoint Transfer Descriptor – “Control” Endpoint Endpoint Transfer Descriptor – “Interrupt In” Endpoint Offset 27-24 – Transfer Control.......................................RW 31 Data Toggle (initial data toggle of this transfer) 0 Data 0 1 Data 1 30-29 Reserved ........................................ always reads 0 28-16 Total Bytes to Transfer...................
VT8237R Data Sheet Endpoint Transfer Descriptor – “Bulk In” Endpoint Endpoint Transfer Descriptor – “Bulk Out” Endpoint Offset 47-44 – Transfer Control.......................................RW 31 Data Toggle (initial data toggle of this transfer) 0 Data 0 1 Data 1 30-16 Total Bytes to Transfer.................
VT8237R Data Sheet Device 17 Function 0 Registers – Bus Control and Power Management All registers are located in the device 17 function 0 configuration space of the VT8237R. These registers are accessed through PCI configuration mechanism #1 via I/O address 0CF8h / 0CFCh. PCI Configuration Space Header Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Revision ID Offset 1-0 - Vendor ID (1106h) .........................................RO Offset 3-2 - Device ID (3227h) .....
VT8237R Data Sheet ISA Bus Control Offset 42 – Line Buffer Control (00h)............................. RW 7 ISA Master DMA Line Buffer Controls whether the DMA line buffer is used. 0 Disable................................................... default 1 Enable. Master DMA waits until the line buffer is full (8 DWords) before transmitting data (bit-6 must also be enabled to insure that there are no coherency issues).
VT8237R Data Sheet Offset 44 – PCI PNP Interrupt Routing INTE/F............RW 7-4 PCI INTF# Routing (see PnP IRQ routing Table 11) 3-0 PCI INTE# Routing (see PnP IRQ routing Table 11) Offset 45 – PCI PNP Interrupt Routing INTG/H ..........RW 7-4 PCI INTH# Routing (see PnP IRQ routing Table 11) 3-0 PCI INTG# Routing (see PnP IRQ routing Table 11) Offset 46 – PCI INTE-F Interrupt Control ....................RW 7-5 Reserved ........................................
VT8237R Data Sheet Miscellaneous Control Offset 4C - IDE Interrupt Routing (04h) ........................RW 7-6 I/O Recovery Time Select When Rx40[6] is enabled, this field determines the I/O recovery time. 00 1 Bus Clock............................................default 01 2 Bus Clock 10 4 Bus Clock 11 8 Bus Clock 5-4 Reserved (do not program) ..................... default = 0 3-2 IDE Secondary Channel IRQ Routing 00 IRQ14 01 IRQ15.....................................................
VT8237R Data Sheet Function Control Offset 50 – Function Control 1 (00h)...............................RW 7 Device 17 Function 6 MC97 0 Enable ....................................................default 1 Disable 6 Device 17 Function 5 AC97 0 Enable ....................................................default 1 Disable 5 Device 16 Function 1 USB 1.1 UHCI Ports 2-3 0 Enable ....................................................default 1 Disable 4 Device 16 Function 0 USB 1.1 UHCI Ports 0-1 0 Enable ............
VT8237R Data Sheet Serial IRQ, LPC, and PC/PCI DMA Control Plug and Play Control - PCI Offset 52 – Serial IRQ & LPC Control (00h) .................RW 7 Reserved ........................................ always reads 0 6 LPC Short Wait Abort 0 Disable ...................................................default 1 Enable. During a short wait, the cycle is aborted after 8Ts. 5 LPC Frame Wait State Time 0 Frame Wait State is 1T...........................
VT8237R Data Sheet GPIO and Miscellaneous Control Offset 58 – Miscellaneous Control 0 (40h) ......................RW 7 PCI DMA Pair B 0 Disable (AD5=GPIO25, AC6=GPIO31)default 1 Enable (AD5=PCREQB, AC6=PCGNTB) 6 Internal APIC 0 Disable (R25=GPIO10,T23=GPIO11,U23=GPI19) 1 Enable ...................................................default (R25=APICD0,T23=APICD1,U23=APICCK) 5 South Bridge Interrupt Cycles Run at 33 MHz 0 Disable ...................................................
VT8237R Data Sheet Offset 5A – DMA Bandwidth Control (00h) ...................RW 7 DMA Channel 7 Bandwidth 0 Normal ...................................................default 1 Improved 6 DMA Channel 6 Bandwidth 0 Normal ...................................................default 1 Improved 5 DMA Channel 5 Bandwidth 0 Normal ...................................................default 1 Improved 4 DMA Single Transfer Mode Bandwidth 0 Normal ...................................................
VT8237R Data Sheet Programmable Chip Select Control Offset 5D-5C – PCS 0 I/O Port Address (0000h)............RW 15-0 PCS 0 I/O Port Address........................... default = 0 Offset 5F-5E – PCS 1 I/O Port Address (0000h) ............RW 15-0 PCS 1 I/O Port Address........................... default = 0 Offset 61-60 – PCS 2 I/O Port Address (0000h) .............RW 15-0 PCS 2 I/O Port Address........................... default = 0 Offset 63-62 – PCS 3 I/O Port Address (0000h) .............
VT8237R Data Sheet Output Control High Precision Event Timers (HPET) Offset 67 – Output Control (04h).....................................RW 7-3 Reserved ........................................ always reads 0 2 FERR Voltage 0 2.5V 1 1.5V ....................................................default 1-0 Reserved ........................................ always reads 0 Offset 68 – HPET Control (00h)...................................... RW 7 High Precision Event Timers 0 Disable..............................
VT8237R Data Sheet ISA Decoding Control Offset 6C – ISA Positive Decoding Control 1 .................RW 7 On-Board I/O (Ports 00-FFh) Positive Decoding 0 Disable ...................................................default 1 Enable 6 Microsoft-Sound System I/O Port Positive Decoding 0 Disable ...................................................default 1 Enable (bits 5-4 determine the decode range) 5-4 Microsoft Sound System I/O Decode Range 00 0530h-0537h ..........................................
VT8237R Data Sheet PCI I/O Cycle Control I/O Pad Control Offset 74 – PCI I/O Cycle Control (00h) .........................RW 7-6 Reserved ........................................ always reads 0 5 Forward LPC Cycles to External PCI Bus 0 Disable ...................................................default 1 Enable 4 Forward LAN Cycles to External PCI Bus 0 Disable ...................................................default 1 Enable 3 Forward USB 2.0 Cycles to External PCI Bus 0 Disable .......................
VT8237R Data Sheet Power Management-Specific Configuration Registers Offset 80 – General Configuration 0 (00h)......................RW 7 Reserved ........................................ always reads 0 6 Sleep Button 0 Disable ...................................................default 1 Sleep Button is on GPI21 / ACSDIN3 pin (V3) 5 Debounce LID and PWRBTN# Inputs for 16ms This bit controls whether the debounce circuit for the LID# and PWRBTN# inputs is enabled to reduce possible noise. 0 Disable ...........
VT8237R Data Sheet Offset 82 - ACPI Interrupt Select ....................................RW 7 ATX / AT Power Indicator .................................RO 0 ATX 1 AT 6 PSON (SUSC#) Gating ........................................RO During system on/off, this status bit reports whether PSON gating state has been completed, 0 meaning that gating is active now and 1 meaning that gating is complete.
VT8237R Data Sheet Offset 85-84 - Primary Interrupt Channel (0000h) ........RW If a device IRQ is enabled as a Primary IRQ, that device’s IRQ can be used to generate wake events. The bits in this register are used in conjunction with: ■ PMIO Rx28[7] – Primary Resume Status ■ PMIO Rx2A[7] – Primary Resume Enable If a device on one of the IRQ’s is set to enable the Primary Interrupt, once the device generates an IRQ, the PMIO Rx28[7] status bit will become 1 to report the occurrence of the Primary IRQ.
VT8237R Data Sheet Offset 8B-88 – Power Management I/O Base .................RW 31-16 Reserved ........................................ always reads 0 15-7 Power Management I/O Register Base Address Port Address for the base of the 128-byte Power Management I/O Register block, corresponding to AD[15:7]. See “Power Management I/O Space Registers” in this document for definitions of the registers in the Power Management I/O Register Block 6-0 0000001b Offset 8C – Host Bus Power Management Control........
VT8237R Data Sheet Offset 93-90 - GP Timer Control (0000 0000h) ..............RW 31-30 Conserve Mode Timer Count Value 00 1/16 second ............................................default 01 1/8 second 10 1 second 11 1 minute 29 Conserve Mode Status This bit reads 1 when in Conserve Mode 28 Conserve Mode This bit controls whether conserve mode (throttling) is enabled.
VT8237R Data Sheet Offset 94 – Power Well Control .......................................WO 7 SMBus Clock Select 0 SMBus Clock from 14.31818 MHz Divider 1 SMBus Clock from RTC 32.768 KHz ... defult 6 Check Power Button Enable for STR/STD Wakeup by PWRBTN# 0 Disable ...................................................default 1 Enable 5 Internal PLL Reset During Suspend 0 Enable ...................................................default 1 Disable 4 SUSST1# / GPO3 Select (Pin Y3) 0 SUSST1# .....................
VT8237R Data Sheet Offset 98 – GP2 / GP3 Timer Control .............................RW 7 GP3 Timer Start On setting this bit to 1, the GP3 timer loads the value defined by Rx9A and starts counting down. The GP3 timer is reloaded at the occurrence of certain events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h).
VT8237R Data Sheet System Management Bus-Specific Configuration Registers SMB GPIO Slave Command Codes Offset D1-D0 – SMBus I/O Base ......................................RW 15-4 I/O Base (16-byte I/O space) ............... default = 00h 3-0 Fixed ................................ always reads 0001b SMBus Command Code 0 – GPIO Slave Input Port...... RO 7-0 Input Data ......................................
VT8237R Data Sheet General Purpose I/O Control Registers Offset E0 – GPI Inversion Control ..................................RW 7-4 GPI[27-24] Input Inversion 0 Non-inverted ..........................................default 1 Inverted 3-0 GPI[19-16] Input Inversion 0 Non-inverted ..........................................default 1 Inverted Offset E1 – GPI SCI / SMI Select ....................................
VT8237R Data Sheet Watchdog Timer Registers Offset EB-E8 – Watchdog Timer Memory Base ............RW 31-8 Watchdog Timer Memory Base [31:8] 7-0 Reserved ........................................ always reads 0 Offset EC – Watchdog Timer Control (00h)...................RW 7-3 Reserved ........................................ always reads 0 2 C3 VID / FID Latency Reduce to 5us 1 Watchdog Timer 0 Disable ...................................................
VT8237R Data Sheet Power Management I/O-Space Registers Basic Power Management Control and Status I/O Offset 1-0 - Power Management Status ................. RWC The bits in this register are set only by hardware and can be reset by software by writing a one to the desired bit position. 15 Wakeup Status ......................................... default = 0 This bit is set when the system is in the suspend state and an enabled resume event occurs.
VT8237R Data Sheet I/O Offset 5-4 - Power Management Control .................RW 15 Soft Resume This bit is used to allow a system using an AT power supply to operate as if an ATX power supply were being used. Refer to the BIOS Porting Guide for implementation details. 0 Disable ...................................................default 1 Enable 14 Reserved ........................................ always reads 0 13 Sleep Enable .................................
VT8237R Data Sheet Processor Power Management Registers I/O Offset 13-10 - Processor & PCI Bus Control ...........RW 31-12 Reserved ........................................ always reads 0 11 Disable PCISTP# When PCKRUN# is Deasserted 0 Enable ....................................................default 1 Disable 10 PCI Bus Clock Run Without Stop 0 PCKRUN# is always asserted................
VT8237R Data Sheet General Purpose Power Management Registers I/O Offset 21-20 - General Purpose Status................... RWC 15 North Bridge SERR# Status 14 USB Wake-Up Status For STR / STD / Soff 13 AC97 Wake-Up Status Can be set only in suspend mode 12 Battery Low Status Set when the BATLOW# input is asserted low. 11 Notebook Lid Status Set when the LID input detects the edge selected by Rx2C bit-7 (0=rising, 1=falling).
VT8237R Data Sheet Generic Power Management Registers I/O Offset 29-28 - Global Status.................................... RWC 15 PCS1 Access Status.................................. default = 0 14 PCS0 Access Status.................................. default = 0 13 GP3 Timer Timeout Status ..................... default = 0 12 GP2 Timer Timeout Status ..................... default = 0 11 SERIRQ SMI Status................................ default = 0 10 Rx5[5] Write SMI Status.........................
VT8237R Data Sheet I/O Offset 2D-2C - Global Control ..................................RW 15-12 Reserved ........................................ always reads 0 11 IDE Secondary Bus Power-Off 0 Disable ...................................................default 1 Enable 10 IDE Primary Bus Power-Off 0 Disable ...................................................default 1 Enable 9 Reserved ........................................ always reads 0 8 SMI Active 0 SMI Inactive.........................................
VT8237R Data Sheet I/O Offset 33-30 - Primary Activity Detect Status....... RWC These bits correspond to the Primary Activity Detect Enable bits in Rx37-34. If the corresponding bit is set in that register, setting of a bit below will cause the Primary Activity Status (PACT_STS) bit to be set (Global Status register Rx28[0]). All bits in this register default to 0, are set by hardware only, and may only be cleared by writing 1s to the desired bit. I/O Offset 37-34 - Primary Activity Detect Enable........
VT8237R Data Sheet I/O Offset 3B-38 - GP Timer Reload Enable ..................RW All bits in this register default to 0 on power up. 31-8 Reserved ........................................ always reads 0 7 GP1 Timer Reload on KBC Access 0 Normal GP1 Timer Operation................default 1 Setting of KBC_STS causes the GP1 timer to reload. 6 GP1 Timer Reload on Serial Port Access 0 Normal GP1 Timer Operation ...............default 1 Setting of COMA_STS or COMB_STS causes the GP1 timer to reload.
VT8237R Data Sheet General Purpose I/O Registers I/O Trap Registers I/O Offset 45 – SMI / IRQ / Resume Status .....................RO 7-5 Reserved ........................................ always reads 0 4 Latest PCSn Status 0 Latest PCSn was an I/O Read 1 Latest PCSn was an I/O Write 3 Serial SMI Status This bit is used to report a Serial-IRQ-generated SMI. 2 Reserved ........................................ always reads 0 1 SMBus IRQ Status This bit is used to report an SMBus SMI.
VT8237R Data Sheet System Management Bus I/O-Space Registers The base address for these registers is defined in RxD1-D0 of the Device 17 Function 0 PCI configuration registers. The System Management Bus I/O space is enabled for access by the system if Device 17 Function 0 RxD2[0] = 1. I/O Offset 00 – SMBus Host Status............................... RWC 7 Reserved ........................................ always reads 0 6 SMB Semaphore ..............................................
VT8237R Data Sheet I/O Offset 02h – SMBus Host Control.............................RW 7 Reserved ........................................ always reads 0 6 Start ........................................ always reads 0 0 Writing 0 has no effect...........................default 1 Start Execution of Command Writing a 1 to this bit causes the SMBus controller host interface to initiate execution of the command programmed in the SMBus Command Protocol field (bits 4-2).
VT8237R Data Sheet I/O Offset 08h – SMBus Slave Control............................RW 7-5 Reserved ........................................ always reads 0 4 SMBus GPIO Slave Enable 0 Disable ...................................................default 1 Enable generation of a resume event upon an external SMBus master generating a transaction with an address that matches the GPIO Slave Address register (I/O offset 0Fh). 3 SMBus Alert Enable 0 Disable ...................................................
VT8237R Data Sheet Device 17 Function 5 Registers - AC97 Audio Controller The audio controller interface is hardware compatible with AC97. The PCI configuration registers for the audio controller are located in the function 5 PCI configuration space. The I/O registers are located in the system I/O space. PCI Configuration Space Header Offset 1-0 - Vendor ID .......................................................RO 15-0 Vendor ID ................. (1106h = VIA Technologies) Offset 3-2 - Device ID............
VT8237R Data Sheet Audio-Specific PCI Configuration Registers Offset 40 – AC Link Interface Status ...............................RO 7-6 Reserved ........................................ always reads 0 5 Codec CID=11b Ready Status ............................RO 0 Codec Not Ready 1 Codec Ready (audio ctrlr can access codec) 4 Codec CID=10b Ready Status ............................RO 0 Codec Not Ready 1 Codec Ready (audio ctrlr can access codec) 3 Reserved ........................................
VT8237R Data Sheet Offset 42 – Function Enable .............................................RW 7-6 Reserved ........................................ always reads 0 5 Function 5 Config Reg Rx2C Writable .............RW 0 Device 17 Function 5 Rx2C-2F RO.......default 1 Device 17 Function 5 Rx2C-2F RW 4-0 Reserved ........................................ always reads 0 Offset 44 – MC97 Interface Control.................................RO Mapped RO to function 5 (RW in func 6) for status reporting.
VT8237R Data Sheet I/O Base 0 Regs – Audio Scatter / Gather DMA DXS Channel 0-3 SGD Registers (x = 0-3) I/O Offset x0 – DXS Channel x SGD Status ................ RWC 7 SGD Active ..........................................................RO 0 SGD has completed or been terminated.default 1 SGD Active 6-5 Reserved ........................................ always reads 0 4 Current SGD Index Equals Stop Index .............RO 0 SGD index not equal to stop index ........
VT8237R Data Sheet I/O Offset x2 – DXS Left Channel x Volume (3Fh)........RW I/O Offset x3 – DXS Right Channel x Volume (3Fh) .....RW 7-6 Reserved (Do Not Program)............always write 0’s 5-0 Volume Control 000000 0 db … … 000111 -10.5 db … … 011111 -46.5 db … … 111111 Muted (instead of -94.5 db) ...............default I/O Offset xF-xC – DXS Chan x SGD Current Count ... RO 31-24 Current SGD Index This field reports the index the SGD engine is currently processing.
VT8237R Data Sheet Multichannel SGD Registers I/O Offset 40 – Multichannel SGD Status .................... RWC 7 SGD Active ..........................................................RO 0 SGD has completed or been terminated.default 1 SGD Active 6-5 Reserved ........................................ always reads 0 4 Current SGD Index Equals Stop Index .............RO 0 SGD index not equal to stop index ........default 1 SGD index being processed equals the stop index.
VT8237R Data Sheet I/O Offset 42 – Multichannel SGD Format.....................RW 7 PCM Format Selects the PCM format used by the controller to process the incoming sample. 0 8-bit .....................................................default 1 16-bit 6-4 Number of Channels Supported 001 One Channel...........................................default 010 Two Channels 100 Four Channels 110 Six Channels All the other values are invalid 3-0 Reserved ........................................
VT8237R Data Sheet Write Channel 0 SGD Registers I/O Offset 60 – Write Channel 0 SGD Status .............. RWC 7 SGD Active ..........................................................RO 0 SGD has completed or been terminated.default 1 SGD Active 6 SGD Paused ..........................................................RO 0 SGD not paused .....................................default 1 SGD Paused 5 Reserved ........................................ always reads 0 4 Current SGD Index Equals Stop Index .............
VT8237R Data Sheet I/O Offset 62 – Write Channel 0 SGD Format ...............RW 7 Reserved (Do Not Program).............. always write 0 6 Recording FIFO 0 Disable ...................................................default 1 Enable 5-0 Reserved ........................................ always reads 0 I/O Offset 63 – Write Channel 0 Input Select.................RW 7-3 Reserved ........................................ always reads 0 2 Input Source Select 0 Line In (Slot 3, 4)..................................
VT8237R Data Sheet Write Channel 1 SGD Registers I/O Offset 70 – Write Channel 1 SGD Status .............. RWC 7 SGD Active ..........................................................RO 0 SGD has completed or been terminated.default 1 SGD Active 6 SGD Paused ..........................................................RO 0 SGD not paused .....................................default 1 SGD Paused 5 Reserved ........................................ always reads 0 4 Current SGD Index Equals Stop Index .............
VT8237R Data Sheet I/O Offset 72 – Write Channel 1 SGD Format ...............RW 7 Reserved (Do Not Program).............. always write 0 6 Recording FIFO 0 Disable ...................................................default 1 Enable 5-0 Reserved ........................................ always reads 0 I/O Offset 73 – Write Channel 1 Input Select.................RW 7-3 Reserved ........................................ always reads 0 2 Input Source Select 0 Line In (Slot 3, 4)..................................
VT8237R Data Sheet Codec Command / Status SGD Registers These registers are used to send commands to the codecs I/O Offset 83-80 – AC97 Controller Cmd (W) / Status (R) This register may be accessed from either function 5 or 6 31-30 Codec ID .........................................................RW 00 Select Codec CID = 00 01 Select Codec CID = 01 10 Select Codec CID = 10 11 Select Codec CID = 11 29 Codec 11 Data / Status / Index Valid.................
VT8237R Data Sheet Device 17 Function 6 Registers - AC97 Modem Controller The modem controller interface is hardware compatible with AC97. The PCI configuration registers for the modem controller are located in the function 6 PCI configuration space. The I/O registers are located in the system I/O space. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h) .........................................RO 15-0 Vendor ID ................. (1106h = VIA Technologies) Offset 3-2 - Device ID (3068h) .........
VT8237R Data Sheet Modem-Specific PCI Configuration Registers Offset 40 – AC Link Interface Status ...............................RO 7-6 Reserved ........................................ always reads 0 5 Codec CID=11b Ready Status ............................RO 0 Codec Not Ready 1 Codec Ready (modem ctrlr can access codec) 4 Codec CID=10b Ready Status ............................RO 0 Codec Not Ready 1 Codec Ready (modem ctrlr can access codec) 3 Reserved ........................................
VT8237R Data Sheet Offset 42 – Function Enable ..............................................RO This register is controlled through function 5 but may be read from function 6. 7-6 5 4-0 Reserved ........................................ always reads 0 Function 5 Config Reg Rx2C Writable ..............RO 0 Device 17 Function 5 Rx2C-2F RO.......default 1 Device 17 Function 5 Rx2C-2F RW Reserved ........................................ always reads 0 Offset D3-D0 – Power Mgmt Capability ......................
VT8237R Data Sheet I/O Base 0 Regs – Modem Scatter / Gather DMA Modem SGD Read Channel Registers I/O Offset 40 – Modem SGD Read Channel Status..... RWC 7 SGD Active ..........................................................RO 0 SGD has completed or been terminated.default 1 SGD Active 6 SGD Paused ..........................................................RO 0 SGD not paused .....................................default 1 SGD Paused 5-4 Reserved ........................................
VT8237R Data Sheet Modem SGD Write Channel Registers I/O Offset 50 – Modem SGD Write Channel Status .......RO 7 SGD Active ..........................................................RO 0 SGD has completed or been terminated.default 1 SGD Active 6 SGD Paused ..........................................................RO 0 SGD not paused .....................................default 1 SGD Paused 5-4 Reserved ........................................ always reads 0 3 SGD Trigger Queued..............................
VT8237R Data Sheet Codec Command / Status SGD Registers These registers are used to send commands to the codecs Offset 83-80 – AC97 Controller Command (W) / Status (R) This register may be accessed from either function 5 or 6 31-30 Codec ID ......................................................... RW 00 Select Codec CID = 00 01 Select Codec CID = 01 10 Select Codec CID = 10 11 Select Codec CID = 11 29 Codec 11 Data / Status / Index Valid..................
VT8237R Data Sheet Device 18 Function 0 Registers - LAN All registers are located in the Device 18 Function 0 PCI configuration space of the VT8237R. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8 / CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h.........................................RO Offset 3-2 - Device ID = 3065h ..........................................RO Offset 5-4 - Command.......................................................
VT8237R Data Sheet Offset 43-42 – Power Mgmt Configuration (0002h)........RO 15-11 Power State In Which LAN Can Assert PME#....... .............................................. default = 0 1xxxx PME# can be asserted from D3C x1xxx PME# can be asserted from D3H xx1xx PME# can be asserted from D2 xxx1x PME# can be asserted from D1 xxxx1 PME# can be asserted from D0 10 D2 PM State 0 Not Supported ........................................default 1 Supported 9 D1 PM State 0 Not Supported ........................
VT8237R Data Sheet LAN I/O Registers Offset 05-00 – Ethernet Address ......................................RW Unless the EEPROM is disabled, the Ethernet Address is loaded to this register from the EEPROM every time the system starts up. Offset 06 – Receive Control (00h) ....................................RW 7-5 Reserved ...................................... Do not program 4 Physical Address Packets Accepted 0 Packets with a physical destination address are not accepted ...................................
VT8237R Data Sheet Offset 08 – Command 0 (00h) ..........................................RW 7 Reserved ........................................ always reads 0 6 Receive Poll Demand ............................... default = 0 If this bit is set to 1, the Receive Descriptor (RD) will be polled once (this bit will be cleared by hardware after the polling is complete) 5 Transmit Poll Demand ............................
VT8237R Data Sheet Offset 0C – Interrupt Status 0 (00h)................................RW 7 CRC or Miss Packet Tally Counter Overflow Set if either counter overflows (both counters are 16 bits) 6 PCI Bus Error Set if PCI bus error occurred. 5 Receive Buffer Link Error Set when there is not enough buffer space for a packet requiring multiple buffers. 4 Reserved ......................................
VT8237R Data Sheet Offset 23-20 – Receive Status (0000 0400h).....................RW 31 Descriptor Owner 0 Descriptor Owned By Host (NIC cannot access descriptor) 1 Descriptor Owned by NIC (NIC can access descriptor) This bit has no default so must be set by the driver at initialization. 30-27 Reserved ........................................ always reads 0 26-16 Received Packet Length ........................ RO, def = 0 15 Received Packet Successfully ................ RO, def = 0 14 Reserved .............
VT8237R Data Sheet Offset 43-40 – Transmit Status (0000 0000h)..................RW 31 Descriptor Owner 0 Descriptor Owned By Host (NIC cannot access descriptor) 1 Descriptor Owned by NIC (NIC can access descriptor) This bit has no default so must be set by the driver at initialization. 30-16 Reserved ........................................ always reads 0 15 Transmit Error ................................ RO, default = 0 0 Transmit Successful ...............................
VT8237R Data Sheet Offset 6C – PHY Address (01h) .......................................RW 7-6 MII Management Polling Timer Interval (Polling PHY) 00 1024 MDC Clock Cycles .......................default 01 512 MDC Clock Cycles 10 128 MDC Clock Cycles 11 64 MDC Clock Cycles MDC is an internal clock with a 960 ns cycle time. 5 Accelerate MDC Speed 0 Normal ...................................................default 1 4x Accelerated 4-0 Extended PHY Device Address..........
VT8237R Data Sheet Offset 70 – MII Management Port Command (00h)......RW 7 MII (PHY) Auto Polling 0 Disable ...................................................default 1 Enable (polling interval determined by Rx6C[7:6] ) 6 PHY Read Every time this bit is set to one, the Phy is read once. The address read is determined by Rx71[4:0] and the data is stored in Rx73-72. 0 Disable ...................................................
VT8237R Data Sheet Offset 79 – Configuration 1 (00h) ....................................RW 7 Transmit Frame Queueing 0 Enable (frames from the PCI bus can be queued in the transmit FIFO – a maximum of 2 packets may be queued) ......................default 1 Disable 6 Data Parity Generation and Checking This bit controls whether PCI parity is enabled. 0 Enable ....................................................
VT8237R Data Sheet Offset 80 – Miscellaneous 1 (00h) ....................................RW 7-4 Reserved ........................................ always reads 0 3 Full Duplex Flow Control 0 Disable ...................................................default 1 Enable 2 Half Duplex Flow Control 0 Disable ...................................................default 1 Enable 1 Soft Timer 0 Status / Start 0 Timer Counting......................................
VT8237R Data Sheet Offset 84 – MII Interrupt Status (00h)......................... RWC The bits in this register correspond to bits in the MII Interrupt Mask register (Rx86). An interrupt is generated when corresponding bits in both registers equal one. 7 6 5 4 3 2 1 0 Power Event Report in Test Mode (RO)...... def = 0 User Defined Host Driven Interrupt ............ def = 0 Reserved ........................................ always reads 0 Suspend Mode MII Polling Status Change..
VT8237R Data Sheet Offset 95-94 – Suspend Mode MII Address (0000h) ......RW 15-0 MII Address During Suspend................. default = 0 Functionally, this field is the same as Rx71[4:0]. However, during suspend state this field is used because Rx71[4:0] cannot be accessed. Offset 96 – Suspend Mode PHY Address (00h) ..............RW 7-0 PHY Address During Suspend ............... default = 0 This field stores the address of the PHY to access during suspend state.
VT8237R Data Sheet Offset A0 – Wake On LAN Control Set (00h) ...............RW Offset A4 – Wake On LAN Control Clear (00h) ............
VT8237R Data Sheet FUNCTIONAL DESCRIPTIONS Refer to ACPI Specification v2.0 and APM specification v1.2 for additional information.
VT8237R Data Sheet System Suspend States and Power Plane Control Processor Bus States The VT8237R supports the complete set of C0 to C3 processor states as specified in the Advanced Configuration and Power Interface (ACPI) specification (and defined in ACPI I/O space Registers 10-15): C0: C1: C2: C3: Normal Operation CPU Halt (controlled by software). Stop Clock. Entered when the Processor Level 2 register (PMIO Rx14) is read. The STPCLK# signal is asserted to put the processor in the Stop Grant State.
VT8237R Data Sheet Power Management Events The suspend state is entered by setting the Sleep Enable bit to 1. Three power plane control signals (SUSA#, SUSB# and SUSC#) are provided to turn off more system power planes as the system moves to deeper power-down states, i.e., from normal operation to POS (only SUSA# asserted), to STR (both SUSA# and SUSB# asserted), and to STD (all three SUS# signals asserted). In particular, the assertion of SUSC# can be used to turn off the VCC supply to the VT8237R.
VT8237R Data Sheet System and Processor Resume Events 3) Generic Global Events defined in the Global Status and Global Enable registers. These registers are mainly used for SMI: • • • • • PCI Bus Clock Run Resume Primary Interrupt Occurance GP0 and GP1 Timer Time Out Secondary Event Timer Time Out Occurrence of Primary Events (defined in the Primary Activity Status and Primary Activity Enable registers) • Legacy USB accesses (keyboard and mouse) - Software SMI Host CPU GCLK b) VSUS-based events.
VT8237R Data Sheet Legacy Power Management Timers In addition to the ACPI power management timer, the VT8237R includes the following four legacy power management timers: GP0 Timer: general purpose timer with primary event GP1 Timer: general purpose timer with peripheral event reload Secondary Event Timer: to monitor secondary events Conserve Mode Timer: Hardware-controlled return to standby The normal sequence of operations for a general purpose timer (GP0 or GP1) is to 1) First program the time base and ti
VT8237R Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Symbol Parameter Min Max Unit Comment –55 125 ºC 0 85 ºC TS Storage Temperature TC Case Operating Temperature VCC Core Voltage –0.5 2.625 Volts 2.5V VSUS25 Suspend Voltage – 2.5V –0.5 VCC + 0.3 Volts 2.5V VSUSUSB Suspend Voltage – USB –0.5 VCC + 0.3 Volts 2.5V VSUSMII Suspend Voltage – LAN –0.5 VCC + 0.3 Volts 2.5V VCCVK V-Link Voltage –0.5 VCC + 0.3 Volts 2.5V VCCPLL PLL Voltage –0.
VT8237R Data Sheet Register Bits Powered by VBAT Register Description RTC Rx0D[7] VBAT Voltage OK F0 Rx96[3:0] CPU Frequency Strapping Value PMIO Rx20[0] GPI0 Status PMIO Rx20[6] INTRUDER# Status PMIO Rx22[2] Enable SCI on KBC PME Asserted Register Bits Powered by VSUS25 Register Description F0 Rx81[2] RTC Enable Gated During Soft Off F0 Rx94[7:0] Power Well Control Register F0 Rx95[3:0] Misc Power Well Control Register PMIO Rx00[15,11,10,8] Wake, Abnormal PowerOff, RTC Alarm, and Power
VT8237R Data Sheet Power Requirements TC = 0 - 85°C VCC = VSUS25 = VSUSUSB = VSUSMII = VCCVK = VCCPLL = VCCUPLL = VCCLAN = 2.5V ±5%, VCC33 = VSUS33 = VCCUSB = VCCMII = 3.3V ±5%, VBAT = 3.3V +0.3 / –0.9V, VSDVREF = VVLVREF = 0.9V ±5%, GND = 0V Symbol Parameter ICC33 ICC Power Supply Current – I/O (3.3V) Power Supply Current – Core (2.5V) ICCVK Power Supply Current – V-Link (2.5V) ISUS33 Power Supply Current – Suspend (3.3V) ISUS25 Power Supply Current – Suspend (2.
VT8237R Data Sheet PACKAGE MECHANICAL SPECIFICATIONS 24.00 REF Ø 1.00(3X) REF 4.00*45º (4X) = Date Code Year = Date Code Week = Chip Version (CD) = Lot Code Part Number 24.00 REF Y W V L 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VT8237R Country of Assembly (TAIWAN or CHINA) YYWWVV CCCCC M C ○ LLLLLLLLLL ○ A B C D E F G H J K L M N P R T U V W Y AA PIN #1 CORNER AB AC AE AD AF Ø 0.10 S C Ø 0.25 S C A S B S Ø 0.60 ±0.
VT8237R Data Sheet 24.00 REF Ø 1.00(3X) REF 4.00*45º (4X) Y W V L 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 = Date Code Year = Date Code Week = Chip Version (CD) = Lot Code 24.00 REF Part Number VT8237R YYWWVV CCCCC M G ○ C ○ LLLLLLLLLL ○ Country of Assembly (TAIWAN or CHINA) Indicates “Lead-Free” Package A B C D E F G H J K L M N P R T U V W Y AA PIN #1 CORNER AB AC AE AD AF Ø 0.10 S C Ø 0.25 S C A S B S Ø 0.60 ±0.
