Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -58- Register Descriptions – VFIR I/O
Technologies, Inc.
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Offset 32 – General Purpose Timer.................................RW
7-0 Timer .............................................. default = 0
The current value of the up-counter is returned when
host reading this register. The running value is reset
to ‘0’ if host write to this register.
The up-counter has a count time of 125us per
increment. The counter will stop incrementing when
it reaches the programmed target value.
Offset 33 – Infrared Configuration .................................RW
7 GPIO0 Source .......................................... default = 0
0 GPIO0 source depends on the IrDA mode
select (Rx10[6:4]) and Infrared Configuration
Register 3 (Rx1Eh) bits 1-0.
1 Select the GPIO0 source as IRRX1
6-2 Reserved ........................................ always reads 0
1 Enable Timer Interrupt
0 Disable ...................................................default
1 Enable
0 Timer Interrupt Pending ...................................WC
0 No timer interrupt pending.....................default
1 Timer interrupt pending
A timer interrupt occurs when the value in the
General Purpose Timer register reaches the
programmed target value. To clear the interrupt,
software writes a 1 to this bit.
Offset 34 – Infrared Transceiver Control Low.............. RW
7GPIO0 ..............................................default = 0
For data input/output and from/to IRRX1 pin. This
bit is controlled by Rx33[7].
6GPIO1.................................................. default = 0
For data input/output and from/to ITMOFF pin.
5-4 Reserved ........................................always reads 0
3 IRRX Pin ......................................................... RO
Used for reading the state of the IRRX pin
2-1 Reserved ........................................always reads 0
0 IRTX Force
0 IRTX pin deasserted.............................. default
1 IRTX pin asserted
Offset 35 – Infrared Transceiver Control High............. RW
7DriveIRRX1
This bit controls and reads the IRRX1 pin.
0 Disable................................................... default
1 Enables mode programming of the Infrared
Transceiver
6DriveITMOFF
0 Disable................................................... default
1 Enables the SCLK pin as an interface signal
for a device that meets revision 1.0 of the
Transceiver Control Serial Interface
specification.
5-0 Reserved ........................................always reads 0