Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -57- Register Descriptions – VFIR I/O
Technologies, Inc.
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Offset 28 – Reset Command (00h)...................................RW
7-4 Reset Command [3:0].........................................WO
Used to send a reset signal to the appropriate
hardware in order to clear a particular status
condition, a counter , or general reset. These bits are
self-clearing (i.e., the programmer does not need to
reset the Reset Command bit value to 0000).
0000 No reset command .................................default
0001 -reserved-
0010 Reset Rx FIFO Pointer
0011 Reset Rx Special Condition Interrupt
0100 Reset Rx Ring Packet Pointer
0101 Reset FIFO Underrun / EOM Latch
0110 Reset Tx FIFO Pointer
0111 Software Reset
1xxx -reserved-
3-0 Reserved ........................................ always reads 0
Offset 29 – Packet Address ..............................................RW
7-0 Rx Packet Address................................... default = 0
Specifies the address value that must be contained in
the address field of incoming packets.
See also the Rx Address Mode setting (BITS 5-4 in
RxControl Register) in the ‘Rx Control ‘ Register.
Offset 2A – Rx Byte Count Low .......................................RO
7-0 Rx Byte Count [7:0]................................. default = 0
Provides a running count (low-order value) of the
number of bytes of data being received. This
information is useful for checking if a reception is in
progress. It should not be used to determine packet
length(RFPwouldbeusedtodothis).
Offset 2B – Rx Byte Count High (00h).............................RO
7-5 Reserved ........................................ always reads 0
4-0 Rx Byte Count [12:8]
Provides a running count (high-order value) of the
number of bytes of data being received. This
information is useful for checking if a reception is in
progress. It should not be used to determine packet
length(RFPwouldbeusedtodothis).
Offset 2C – Rx Ring Packet Pointer Low........................ RO
7-0 Ring Frame Pointer [7:0] ........................ default = 0
Used in back-to-back packet reception to provide the
end-of-packet pointer value (i.e., a pointer to the last
byte of a frame received in the receive buffer).
The order of byte access to the Ring Packet Pointer is
critical for obtaining a valid pointer value. The
programmer must ensure that the low byte is read
first, followed by the high byte.
Offset 2D – Rx Ring Packet Pointer High (00h) ............. RO
7 Reserved ........................................always reads 0
6-0 Rx Frame Pointer [14:8]
Used in back-to-back packet reception to provide the
end-of-packet pointer value (i.e., a pointer to the last
byte of a frame received in the receive buffer).
The order of byte access to the Ring Packet Pointer is
critical for obtaining a valid pointer value. The
programmer must ensure that the low byte is read
first, followed by the high byte.
Offset 2E – Tx Byte Count Low ...................................... RW
7-0 Tx Byte Count [7:0] ................................. default = 0
Provides a running count of the number of bytes of
remaining to be transmitted. Before enabling
transmission, software loads this register with the
low-order byte length of the data packet. Each time
TxFIFO is written to, the value of this counter
decrements by 1. When the counter reaches zero, the
transmitter ceases to make DMA requests.
Transmission continues until TxFIFO is depleted.
Offset 2F – Tx Byte Count High ..................................... RW
7-4 Reserved ........................................always reads 0
3-0 Tx Byte Count [11:8] ....................... default = 0000b
Provides a running count of the number of bytes
remaining to be transmitted. Before enabling
transmission, software loads this register with the
high-order byte length of the data packet. Each time
the TxFIFO is written to, the value of this counter
decrements by 1. When the counter reaches zero, the
transmitter ceases to make DMA requests.
Transmission continues until the TxFIFO is depleted.