Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -56- Register Descriptions – VFIR I/O
Technologies, Inc.
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Offset 26 – Rx Control (40h)............................................RW
7-6 RxFIFO Level
An interrupt occurs when bit-1 (Rx FIFO Ready
Interrupt) is set and the Receive FIFO level reaches
the following setting (settings depend on FIFO Size
bits 1-0):
00 Full level ................................................default
01 1/4
10 1/2
11 3/4
5-4 Rx Address Mode [1:0]
Specifies the type of address filtering to apply for
determining which receive packets to accept.
00 All packets are received with no filter applied
.....................................................default
01 Packets with addresses that match the address
aetting in bits 7-1
of the Packet Address
register will be received
10 Packets with addresses that match the address
aetting in bits 7-4
of the Packet Address
register will be received
11 Packets with addresses that match the address
aetting in bits 7-0
of the Packet Address
register will be received
3-2 Reserved ........................................ always reads 0
1 Rx FIFO Ready Interrupt
0 Disable ...................................................default
1 Enable
0 Rx Special Condition Interrupt
0 Disable ...................................................default
1 Enable the following receive special condition
interrupts:
– Overrun
– CRC Error
– End of Packet (EOF)
– PHY Error: The physical layer detected an
encoding error.
– Max Length: The maximum length packet was
encountered.
–SIRBad
Offset 27 – Rx Status......................................................... RO
7 PHY Error .............................................. default = 0
‘1’ indicates the physical layer has detected an error
encoding. This bit is automatically cleared upon
detection of the ending/stop flag of the next incoming
packet.
6 CRC Error .............................................. default = 0
‘1’ indicates that a CRC error occurred. The CRC is
checked against known constants for either 16 or 32
bits depending on the length of the CRC chosen in
the IRCONFIG0 register (Rx10h). Valid for VFIR,
MIR, and FIR modes only. This bit is automatically
cleared upon detection of the ending/stop flag of the
next incoming packet.
5 FIFO Overrun Interrupt ......................... default = 0
‘1’ indicates that the RxFIFO overflowed. This bit is
cleared by a reset Rx Special Condition Interrupt
command from the Reset Command Register.
4 EOF (End of Packet)................................ default = 0
‘1’ indicates that a packet has completed reception.
This bit is automatically cleared upon starting of the
next packet.
3 Rx Data Available
0 RxFIFO is empty................................... default
1 RxFIFO is not empty (i.e., the FIFO contains
receive data).
This bit doesn’t cause an interrupt.
2 Reserved ........................................always reads 0
1RxMaxLength......................................... default = 0
‘1’ indicates the maximum length packet was
encountered. For SIR this means the packet was
closed and another will be open without any data
being truncated. In other modes once the maximum
length is hit, no other data will be received. This bit
is automatically cleared upon starting the next packet.
0SIRBad .............................................. default = 0
If the SIR filter is on and this bit is ‘1’, it indicates
that a begin flag is seen followed by valid data and
then followed by another begin flag (without an end
flag). This bit is automatically cleared upon starting
of the next packet.