Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -55- Register Descriptions – VFIR I/O
Technologies, Inc.
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Offset 24 – Tx Control 2 (40h) .........................................RW
7 Force Underrun
0 Disable ...................................................default
1 Enable an underrun on this packet for testing
(for an underrun occur, the Tx count should be
greater than 18 bytes)
6 Transmit CRC
0 Setting for SIR mode or bridging application
where CRC should not be generated by
hardware
1 Enable Tx CRC for synchronous packets ... def
5 Bad CRC
0 Disable ...................................................default
1 Send out inverted CRC or bad CRC (used to
test the receiver CRC verification hardware)
4 Need Pulse
0 Disable ...................................................default
1 Transmit an indication pulse after this packet
has been transmitted
3 Request To Clear Enable Tramit
0 Disable ...................................................default
1 Enables the hardware to clear the ENTX bit
(Rx10[5]) after this packet is completed.
Should be set on a least packet of a transmit
sequence.
2-0 Early EOM Interrupt Level.............. default = 000b
Specifies the number of bytes that must remain in Tx
Byte Count before an Early EOM interrupt is
generated. The reason for having an interrupt occur
before transmission has actually completed is to
allow enough time for the software to enter the
proper interrupt handler routine, turn the DMA
channel around for reception (Single DMA mode), or
prepare for another back-to-back transmission. Once
in the interrupt handler routine, the software can poll
the EOM bit in TxStatus Register to determine
exactly when the transmission ends.
000 Interrupt by EOM...................................default
001 EOM intr occurs when remaining count = 16
010 EOM intr occurs when remaining count = 32
011 EOM intr occurs when remaining count = 64
100 EOM intr occurs when remaining count = 128
101 EOM intr occurs when remaining count = 256
110 EOM intr occurs when remaining count = 512
111 EOM intr occurs when remaining count =
1024
Offset 25 – Tx Status ......................................................... RO
7-4 Reserved…..........................................always reads 0
3 TxFIFO Underrun ................................... default = 0
‘1’ indicates that the TxFIFO ran out of data before
the transmitter could finish transmitting all the data
(i.e., TxFIFO is empty, and the Tx Byte Count value
is greater than zero). This bit must be reset by an
explicit FIFO Underrun/EOM Latch command.
2 EOM (End of Message)............................ default = 0
‘1’ indicates transmission completed successfully.
The EOM interrupt occurs immediately after the
CRC and ending flag have been transmitted. The
EOM bit would be clear by a reset FIFO
Underrun/EOM Latch command from the Reset
Command Register.
1TxFIFOReady.........................................default = 0
‘1’ indicates that the Transmit FIFO is ready for
more data transfers. When the En_TXFIFO_Ready
Int bit (Bit 6 of the ‘TxControl 1’ Register) is set, an
interrupt is generated whenever this condition
becomes true.
0 Early End of Message (EOM) ................. default = 0
‘1’ indicates that the Tx Byte Count has reached the
count level set by the Early EOM Interrupt Level
(Bits 2:0 in ‘TxControl 2’ Register). This bit is
cleared by reading TxStatus.