Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -54- Register Descriptions – VFIR I/O
Technologies, Inc.
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Offset 21 – Host Status (00h) ............................................RO
7 Reserved ........................................ always reads 0
6 Timer Interrupt ................................................... RO
‘1’ indicates that a timer interrupt is pending.
5 Tx Interrupt ......................................................... RO
‘1’ indicates that a transmitter interrupt is pending.
4 Rx Interrupt ......................................................... RO
‘1’ indicates that a receiver interrupt is pending. The
following conditions clear the Rx Interrupt condition:
n Reading the Rx Ring Packet Counter Low
Register
n Issuing a Reset Rx Special Condition Interrupt
command
n Hardware Reset
n Software Reset
3-1 Interrupt Identification [2:0] .............................. RO
This 3-bit identification code provides an alternative
method for identifying the interrupt source by
indicating the interrupt type and priority level.
Interrupt Type
Priority
0xx -reserved- n/a
100 Rx Special Condition Highest
– FIFO Overrun
– CRC Error
– End of Packet (EOF)
– Phy Error
– Max Length
–BadSIR
101 Rx Data Available Second
110 Tx Buffer Empty Third
111 Tx Special Condition Fourth
– FIFO Underrun
–EOM
–EarlyEOM
0HostBusy.......................................................... RO
0 IR controller host interface is not processing a
transaction.
1 IR controller host interface is in the process of
completing a transaction (any transmit or
receive).
Offset 22 – Miscellaneous Control .................................. RW
7TransmitDMAEnable
0 Disable................................................... default
1 Enable DREQ1 (if dual DMA channel is
selected) as a transmit DMA channel
6 Receive DMA Enable
0 Disable the receive DMA channel (but
DREQ0 is used also for transmit if both of bits
of single DMA channel DREQ0 and Transmit
DMA Enable are set)............................. default
1 Enable DREQ0 as a receive DMA channel
(DREQ0 is also used for the transmit DMA
channel if a single DMA channel is selected)
5 Swap DMA Channel
0 Disable................................................... default
1 Enable swap of DREQ0 and DREQ1
4 Internal Loopback
0 Disable................................................... default
1 Enable internal loopback at the physical layer
3 Enable Transmit on Loop
0 Disable................................................... default
1 Enable transmission to LED when internal
loopback is enabled
2-0 Reserved ........................................always reads 0
Offset 23 – Transmit Control 1 (00h) ............................. RW
7 Reserved ........................................always reads 0
6 Transmit FIFO Ready Interrupt
0 Disable................................................... default
1 Enable TxFIFO Ready interrupt (when
TXFIFO reaches its threshold level).
5 Transmit FIFO Underrun/EOM Interrupt Enable
0 Disable................................................... default
1 Enable TxFIFO Underrun and EOM
interrupts.
4-3 Transmit FIFO Level
An interrupt occurs when bit-6 (Transmit FIFO
Ready Interrupt) is set and the Transmit FIFO level is
below the trigger level per the following setting
(settings depend on the FIFO size):
00 FIFO Full............................................... default
01 FIFO 3/4 Full
10 FIFO 1/2 Full
11 FIFO 1/4 Full
2-0 Reserved ........................................always reads 0