Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -53- Register Descriptions – VFIR I/O
Technologies, Inc.
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Offset 1E – Infrared Configuration 3 (00h)....................RW
7-6 Filter Select
00 Highest filter ..........................................default
01 Medium high filter
10 Medium low filter
11 Lowest filter
5 FIR Adjacent Pulse Width Packet Circuit
0 Enable ....................................................default
1Disable
4 FIR Pulse Width Adjustment.
0 Enable ....................................................default
1Disable
3-2 Reserved ............................................. always reads 0
1 Number of Receive Pins
One receive pin instead of two.
0 2 receiver paths. (use IRRX for FIR and
IRRX1 for SIR)................................................. default
1 1 receiver (i.e., use IRRX for FIR and SIR)
0 Invert RX Mode
When one receive pin is configured, this bit defines
polarity for the mode pin to the Optical module.
0 Slow speed is chosen by a logic ‘0’ .......default
1 Slow speed is chosen by a logic ‘1’
Offset 20 – Host Control .................................................. RW
7 Interrupt Enable
0 Disable................................................... default
1 Enables all FIR Controller interrupts
6 Transmit Start.......................................... default = 0
Start execution of transmit. Logic 1 initiates the
transmitter logic of controller to execute the
transmitting mode of IR programmed in the infrared
configuration registers and also need to setup DMA
and all necessary registers prior to writing a 1 to this
bit position. Writing a 0 has no effect. This bit
always reads 0. The Host_Busy bit can be used to
identify when the IR host controller has finished
executing the Transmission.
5 Receive Start…......................................... default = 0
Start receive execution. Logic 1 initiates the
controller receiver logic to execute the receiving
mode of IR programmed in the infrared configuration
registers. DMA and all necessary registers need to
be set up prior to writing a 1 to this bit position.
Writing a 0 has no effect. This bit always reads 0.
The Host_Busy bit can be used to identify when the
IR host controller has finished executing the
reception.
4 Clear Rx Interrupt
0 Don’t clear............................................. default
1 Clear Rx Interrupt output
3-0 Reserved..............................................always reads 0