Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -51- Register Descriptions VFIR I/O
Technologies, Inc.
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IrDA (VFIR) Host Controller I/0 Registers
These registers are normally accessed at I/O port addresses
starting at E800h (see LDN C Rx61-60 for the VFIR
Controller I/O Port Base setting).
Offset 10 Infrared Configuration Low 0......................RW
7 CRC Length
0 32-bit CRC.............................................default
1 16-bit CRC
6FIRMode
0 Disable ...................................................default
1 Enable
5MIRMode
0 Disable ...................................................default
1 Enable
4SIRMode
0 Disable ...................................................default
1 Enable
3 SIR Configuration Enable
0 Disable ...................................................default
1 Enables SIR Byte FILTER on the receiver
when SIR mode bit is set
2 SIR Test
0 Disable ...................................................default
1 Enables SIR FILTER to be used when not in
SIR mode
1 Invert Transmit LED
0 Do not invert ..........................................default
1 Invert TX LED (TXD pin) output
0 Invert Receive LED
0 Do not invert ..........................................default
1 Invert RX LED (FIRRXD and SIRRXD) input
Offset 11 Infrared Configuration High 0 .................... RW
7-6 Reserved.….........................................always reads 0
5 VFIR Mode (16 Mbit)
0 Disable................................................... default
1 Enable
4 Transmit Enable
0 Disable................................................... default
1 Enables the transmitter at the physical layer
3 Receive Enable
0 Disable................................................... default
1 Enables the receiver at the physical layer
(The receiver will not be enabled if ENTX is
on and loop back is not active).
2 Memory Sequencer Enable
0 Disable................................................... default
1 Enable the memory sequencer to allow
memory access through by ISA DMA
controller
1 Receive Small / Runtime Packets (<4 Bytes)
0 Disable................................................... default
1 Enable (used for SIR mode only)
0FIFOSize
0 64 bytes of FIFO level for each of Rx and Tx
.................................................... default
1 32 bytes of FIFO level for each of Rx and Tx