Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -49- Register Descriptions – Hardware Monitor I/O
Technologies, Inc.
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Offset 4D – Temperature Resolution ...............................RO
7-6 Temp of UCH5
For thermal input of UCH5: 10-bit temperature
resolution (LSB TEMP [1:0]).
5-4 Temp of UCH4
For thermal input of UCH4: 10-bit temperature
resolution (LSB TEMP [1:0]).
3-2 Temp of UCH3
For thermal input of UCH3: 10-bit temperature
resolution (LSB TEMP [1:0]).
1-0 Temp of UCH2
For thermal input of UCH2: 10-bit temperature
resolution (LSB TEMP [1:0]).
Offset 4E – Over Temperature Control (0Fh)............... RW
3 Over Temperature of UCH5 ................... default = 1
A one disables the UCH5 as input source to activate
the Over Temperature (OVTEMP_) occurs. (This bit
is independent with any interrupt status bit).
(Powerup default = 1).
2 Over Temperature of UCH4 ................... default = 1
A one disables the UCH4 as input source to activate
the Over Temperature (OVTEMP_) occurs. (This bit
is independent with any interrupt status bit).
(Powerup default = 1).
1 Over Temperature of UCH3 ................... default = 1
A one disables the UCH3 as input source to activate
the Over Temperature (OVTEMP_) occurs. (This bit
is independent with any interrupt status bit).
(Powerup default = 1).
0 Over Temperature of UCH2 ................... default = 1
A one disables the UCH2 as input source to activate
the Over Temperature (OVTEMP_) occurs. (This bit
is independent with any interrupt status bit).
(Powerup default = 1).