Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -45- Register Descriptions – Hardware Monitor I/O
Technologies, Inc.
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Offset 43 – Interrupt Mask 1 ...........................................RW
7 FAN2 .............................................. default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
6 FAN1 .............................................. default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
5 Over Temp 1(Intel Thermal TIN0) ....... default = 0
A one disables the Temp1 as input source to activate
Over Temperature (OVTEMP#) indication. (This bit
is independent of any interrupt status bit).
4Temp1(TIN0)......................................... default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt (for Intel type thermal diode).
3 +5V (UCH4) ............................................. default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
2 +3.3V (Internal VDD).............................. default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
1 +VCCP (UCH3) ....................................... default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
0 +2.5V (UCH2) .......................................... default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
Offset 44 – Interrupt Mask 2 ...........................................RW
7-6 Reserved ........................................ always reads 0
5 Over Temp2 (UCH1 & TIN1)................. default = 0
A one disables Temp2 as an input source to activate
Over Temperature (OVTEMP#) indication. (This bit
is independent of any interrupt status bit.
4 Chs_sec (Chassis Intrusion).................... default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
3 Temp2 (UCH1 & TIN1) .......................... default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
2-1 Reserved ........................................ always reads 0
0 +12V (UCH5) .......................................... default = 0
A one disables the corresponding interrupt status bit
for the INT interrupt.
Offset 45 – VID (00h) ........................................................ RO
7 Over Temperature
0 OVTEMP# output active (low)
1 OVTEMP# output inactive (high)
6 Over Voltage
0 OVOLT output inactive (low)
1 OVOLT output active (high)
5 Over Fan
0 OVFAN output inactive (low)
1 OVFAN output active (high)
4-0 VID[4-0]
These bits read the state of the Voltage ID readouts
from the CPU.
Offset 46 – Over Voltage & Over Fan Control (FFh) .. RW
7 Reserved ........................................always reads 1
6 Over FAN of FAN2 .................................. default = 1
A one disables FAN2 as an input source to activate
the Over FAN (OVFAN) indication. (This bit is
independent of any interrupt status bit).
5 Over FAN of FAN1 .................................. default = 1
A one disables FAN1 as an input source to activate
the Over FAN (OVFAN) indication. (This bit is
independent of any interrupt status bit).
4 Over Voltage of UCH5 ............................ default = 1
A one disables UCH5 as an input source to activate
the Over Voltage (OVOLT) indication. (This bit is
independent of any interrupt status bit).
3 Over Voltage of UCH4............................. default = 1
A one disables UCH4 as an input source to activate
the Over Voltage (OVOLT) indication. (This bit is
independent of any interrupt status bit).
2 Over Voltage of UCH3............................. default = 1
A one disables UCH3 as an input source to activate
the Over Voltage (OVOLT) indication. (This bit is
independent of any interrupt status bit).
1 Over Voltage of UCH2............................. default = 1
A one disables UCH2 as an input source to activate
the Over Voltage (OVOLT) indication. (This bit is
independent of any interrupt status bit).
0 Over Voltage of UCH1............................. default = 1
A one disables UCH1 as an input source to activate
the Over Voltage (OVOLT) indication. (This bit is
independent of any interrupt status bit)