Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -44- Register Descriptions – Hardware Monitor I/O
Technologies, Inc.
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Offset 40 – Configuration (08h).......................................RW
7 Initialization
0 Power-on default....................................default
1 Restore powerup default values to the
Configuration register, Interrupt Status
register, Interrupt Mask registers, Fan Divisor
/ RST# / OS# register, and OS# Configuration
/ Temperature resolution register. This bit
automatically clears itself.
6CIPulse .............................................. default = 0
A one outputs a minimum 20ms active low pulse on
the Chassis Intrusion pin. This register bit clears
itself once the pulse is output.
5AFEDataOut
0 Disable ...................................................default
1 Enable AFE test data output on ATEST pin
4AFEEnable
0 Enable ....................................................default
1Disable
3 INT Clear ................................................. default = 1
During the Interrupt Service Routine (ISR) this bit-
asserted logic 1 clears the INT output without
affecting the contents of the Interrupt Status Register.
The device will stop monitoring and resume after
clearing this bit.
2 Reserved ........................................ always reads 0
1 INT Output
0 Disable ...................................................default
1 Enable
0Start .............................................. default = 0
0 Put chip in standby mode.......................default
1 Enable startup of hardware monitoring
At startup, limit checking functions and scanning
begins. Note: Set all HIGH and LOW LIMITS into
the LANDesk Configuration Manager ASIC prior to
turning on this bit.
Caution: The outputs of the Interrupt pins will not be cleared
if the user writes a zero to this location after an interrupt has
occurred (see “INT Clear” bit).
Offset 41 – Interrupt Status 1........................................... RO
7 FAN2 Error (FANIN1) ............................ default = 0
A one indicates that a fan count limit has been
exceeded.
6 FAN1 Error (FANIN0) ............................ default = 0
A one indicates that a fan count limit has been
exceeded.
5 Reserved ........................................always reads 0
4 Temp1 Error (Thermal IN0) .................. default = 0
Low Hot Temperature limit has been exceeded. Only
‘Default Interrupt’ and ‘One-Time Interrupt’ modes
are supported. The mode is set by bit 0 and 1 of the
Temperature Resolution Register (for Intel type
thermal diode).
3 +5V Error (UCH4)................................... default = 0
A one indicates a High or Low limit has been
exceeded.(also CH5 of AFE).
2 +3.3V Error (Internal VDD) ................... default = 0
A one indicates a High or Low limit has been
exceeded.(also CH7 of AFE).
1 VCCP Error (UCH3)............................... default = 0
A one indicates a High or Low limit has been
exceeded.(also CH4 of AFE).
0 +2.5V Error (UCH2)................................default = 0
A one indicates a High or Low limit has been
exceeded. (also CH3 of AFE).
Offset 42 – Interrupt Status 2........................................... RO
7 Temp3 Error (THERMAL IN2)............. default = 0
Reserved for Internal thermal diode.
6-5 Reserved .............................................always reads 0
4 Chassis Error (CHASSIS IN).................. default = 0
A one indicates Chassis Intrusion has gone high.
3 Temp2 Error (UCH1 or THERMAL IN1) .. def = 0
A one indicates a High or Low limit has been
exceeded. (also for CH2 of AFE).
2 Reserved .............................................always reads 0
1 –12V / VCCP2 Error (AIN5)................... default = 0
Reserved
0 +12V Error (UCH5) ................................. default = 0
A one indicates a High or Low limit has been
exceeded.
Note: Any time the Status Register is read, the conditions (in
other words, Register) that are read are automatically reset. In
the case of voltage priority indication, if two or more voltages
were out of limits, then another indication would
automatically be generated if it was not handled during the
ISR. In the Control Register, the errant voltage may be
disabled until the operator has time to clear the errant
condition or set the limit higher or lower.