Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -42- Register Descriptions – Hardware Monitor I/O
Technologies, Inc.
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Hardware Monitor I/0 Registers
These registers are normally accessed at I/O port addresses
starting at EC00h (see LDN B Rx61-60 for the Hardware
Monitor I/O Port Base setting).
Offset 10 –SELD0 [7:0] for AFE as Digital filter
parameter SELD [7:0] .....................................................RW
Offset 11 – SELD1 [7:0] for SELD [15:8] ......................RW
Offset 12 – SELD2 [7:0] for SELD [19:16] .....................RW
Offset 13 –Analog data D [15:8] .....................................RW
Offset 14 –Analog data D [7:0] ........................................RW
Offset 15 –Digital data D [7:0] .........................................RW
Offset 16 – Channel Counter ...........................................RW
Offset 17 – Data Valid & Channel Indications...............RW
Offset 18 –SMBus Control Register (Noise Avoiding) ..RW
Offset 19 –AFE Control ...................................................RW
7 AFE Internal current source select ........ default = 0
6 AFE Oscillator output select................... default = 0
5 AFE Clock source select.......................... default = 0
4 AFE Clock frequency select ................... default = 0
3 Negative voltage input select................... default = 0
2 Cycle time select....................................... default = 0
1 Cycle type select ....................................... default = 0
0 Data input select ..................................... default = 0
Offset 1A –AFE Test Control ..........................................RW
7 BIST Enabled........................................... default = 0
6-4 BIST mode select ..................................... default = 0
3-1 Reserved ............................................. always reads 0
0 Enable channel setting ............................ default = 0
Offset 1B – Channel Setting ............................................RW
7-4 Reserved ........................................ always reads 0
3-0 Channel Setting….................................. ..default = 0
Offset 1D –Hot Temp Limit (H) (For Temp reading 3) RW
Offset 1E–Hot Temp Hysteresis Limit (Low) ................ RW
Offset 1F –Temp reading 1 (for Intel Thermal Diode) . RW
Offset 20 – Temperature Reading 3 (Reserved for Internal
Thermal Diode)................................................................. RW
Offset 21 –UCH 1 Default as Thermal input
(Temperature reading 2) that setting for NTC type
thermistor input................................................................ RW
Offset 22 –UCH 2 ,Default setting for Voltage inputs... RW
Offset 23 – UCH 3 Default setting for Voltage inputs... RW
Offset 24 – UCH 4 Default setting for Voltage inputs... RW
Offset 25 – UCH 5 Default setting for Voltage inputs... RW
Offset 26 – +3.3V (Internal VDD) ................................... RW
Offset 27 – +2.5V_Sense/Vccp2 or –12v (Reserved)...... RW
Offset 29 – FAN1 reading ................................................ RW
Note: This location stores the number of counts of the internal
clock per-revolution.
Offset 2A – FAN 2 reading .............................................. RW
Note: This location stores the number of counts of the internal
clock per-revolution.