Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -39- Register Descriptions – Wake Up Control I/O
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Offset 08 – GPIO Port 0 Data ..........................................RW
7-0 GPIO Data 0......................................... default = 00h
If this register as GPO, it should be program with the
value of each bit determines the value drive on the
corresponding GPIO pin when its output buffer is
enabled. Writing to the bit latches the written data.
Reading the bit returns its value, regardless of the pin
value.
If as GPI and reads each bit should returns the value
of the corresponding GPIO pin when its output
buffer is disabled, regardless of the write value.
This direction (I/O) configuration of GPIO pin is
decided by register of GPOUTCFG0(Reg. 20h) and
pin function configured by Global Register offset
25h.
Offset 09 – GPIO Port 1 Data ..........................................RW
7-0 GPIO Data 0......................................... default = 00h
If this register as GPO, it should be program with the
value of each bit determines the value drive on the
corresponding GPIO pin when its output buffer is
enabled. Writing to the bit latches the written data.
Reading the bit returns its value, regardless of the pin
value.
If as GPI and reads each bit should returns the value
of the corresponding GPIO pin when its output
buffer is disabled, regardless of the write value.
The direction (I/O) configuration of the GPIO pins is
decided by Rx22 and pin functions are configured by
Global Register offset 26h.
Offset 0A – Module IRQ Status 0 .................................... RO
7-0 Module IRQ [7:0] Status
This register shows the status of device IRQs
(MIRQx) 7-0 detection. The MIRQ interrupts are
enabled by corresponding bits of Rx0C.
0 IRQx undetected.................................... default
1 IRQx detected
These bits are set by hardware and can only be
cleared when Module IRQ events have finished their
service
Offset 0B – Module IRQ Status 1 .................................... RO
7-0 Module IRQ [15:8] Status
This register shows the status of device IRQs
(MIRQx) 15-8 detection. The MIRQ interrupts are
enabled by corresponding bits of Rx0D.
0 IRQx undetected.................................... default
1 IRQx detected
These bits are set by hardware and can only be
cleared when Module IRQ events have finished their
service
Offset 0C – Module IRQ Enable 0 .................................. RW
7-0 Module IRQ [7:0] Enable
This register controls the status function of module
IRQs 7-0. Each bit enables the corresponding bit of
Rx0A.
0 IRQx undetected.................................... default
1 IRQx detected
Offset 0D – Module IRQ Enable 1 .................................. RW
7-0 Module IRQ [15:8] Enable
This register controls the status function of module
IRQs 15-8. Each bit enables the corresponding bit of
Rx0B.
0 IRQx undetected.................................... default
1 IRQx detected