Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -30- Register Descriptions – Serial Port 1
Technologies, Inc.
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Serial Port 1 I/O Registers
These registers are normally accessed at standard Parallel Port
I/O addresses 3F8-3FFh (see LDN 1 Rx61-60 for the Parallel
Port I/O Base setting).
Offset 0 – Transmit / Receive Buffer...............................RW
7-0 Serial Data
Offset 1 – Interrupt Enable..............................................RW
7-4 Undefined ..........................................always read 0
3 Interrupt on Handshake Input State Change
2 Intr on Parity, Overrun, Framing Error or Break
1 Interrupt on Transmit Buffer Empty
0 Interrupt on Receive Data Ready
Offset 1-0 – Baud Rate Generator Divisor .....................RW
15-0 Divisor Value for Baud Rate Generator
Baud Rate = 115,200 / Divisor
(e.g., setting this register to 1 selects 115.2 Kbaud)
Offset 2 – Interrupt Status ................................................RO
7-3 Undefined ..........................................always read 0
2-1 Interrupt ID (0=highest priority)
00 Priority 3 (Handshake Input Changed State)
01 Priority 2 (Transmit Buffer Empty)
10 Priority 1 (Data Received)
11 Priority 0 (Serialization Error or Break)
0 Interrupt Pending
0 Interrupt Pending
1 No Interrupt Pending
Offset 2 – FIFO Control ...................................................WO
Offset 3 – UART Control .................................................RW
7 Divisor Latch Access
0 Access xmit / rcv & int enable regs at 0-1
1 Access baud rate generator divisor latch at 0-1
6 Break
0 Break condition off
1 Break condition on
5-3 Parity
000 None
001 Odd
011 Even
101 Mark
111 Space
2StopBits
01
12
1-0 Data Bits
00 5
01 6
10 7
11 8
Offset 4 – Handshake Control......................................... RW
7-5 Undefined ......................................... always read 0
4 Loopback Check
0 Normal operation
1 Loopback enable
3 General Purpose Output 2 (unused in 82C686B)
2 General Purpose Output 1 (unused in 82C686B)
1 Request To Send
0Disable
1 Enable
0 Data Terminal Ready
0Disable
1 Enable
Offset 5 – UART Status ................................................... RW
7 Undefined ......................................... always read 0
6 Transmitter Empty
0 1 byte in transmit hold or transmit shift
register
1 0 bytes transmit hold and transmit shift regs
5 Transmit Buffer Empty
0 1 byte in transmit hold register
1 Transmit hold register empty
4 Break Detected
0 No break detected
1 Break detected
3 Framing Error Detected
0 No error
1 Error
2 Parity Error Detected
0 No error
1 Error
1 Overrun Error Detected
0 No error
1 Error
0 Received Data Ready
0 No received data available
1 Received data in receiver buffer register
Offset 6 – Handshake Status ........................................... RW
7 DCD Status (1=Active, 0=Inactive)
6 RI Status (1=Active, 0=Inactive)
5 DSR Status (1=Active, 0=Inactive)
4 CTS Status (1=Active, 0=Inactive)
3 DCD Changed (1=Changed Since Last Read)
2 RI Changed (1=Changed Since Last Read)
1 DSR Changed (1=Changed Since Last Read)
0 CTS Changed (1=Changed Since Last Read)
Offset 7 – Scratchpad....................................................... RW
7 Scratchpad Data