Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -27-Register Descriptions – LDN 9-D Watchdog, Wakeup, HWM, IR, ROM
Technologies, Inc.
We Connect
We ConnectWe Connect
We Connect
Watch Dog Registers (LDN 9)
Offset 30 – Watch Dog Activate (00h).............................RW
7-1 Reserved .............................................. default = 0
0 Watch Dog Function….……................... default = 0
0 Disable ...................................................default
1 Enable
Offset 61-60 – Watch Dog I/O Base Address (EA00h) ..RW
15-4 Watch Dog I/O Base ......................... default = EA0h
3-0 Reserved ........................................ always reads 0
Offset 70 – Watch Dog IRQ Select ..................................RW
7-4 Reserved ........................................ always reads 0
3-0 Watch Dog IRQ Select ............................ default = 0
Offset F0 – Watch Dog Timer Configuration.................RW
7-4 Reserved ........................................ always reads 0
3-0 Watch Dog Timer Pin Configuration .... default = 0
Wake-Up Control Registers (LDN A)
Offset 30 – WUC Activate (00h) ......................................RW
7-1 Reserved ........................................ always reads 0
0 Wake Up Control (WUC) Function
0 Disable ...................................................default
1 Enable
Offset 61-60 – WUC I/O Base Address (EB00h) ............RW
15-4 WUC I/O Base….……...................... default = EB0h
3-0 Reserved ........................................ always reads 0
Offset 70 – WUC IRQ Select (00h)..................................RW
7-4 Reserved ........................................ always reads 0
3-0 WUC IRQ Select.….……........................ default = 0
Hardware Monitor Registers (LDN B)
Offset 30 – Hardware Monitor Activate (00h) ...............RW
7-1 Reserved ........................................ always reads 0
0 Hardware Monitor Function .................... default = 0
0 Disable ...................................................default
1 Enable
Offset 61-60 – HWM I/O Base Address (EC00h)...........RW
15-8 HWM I/O Base.................................... default = ECh
7-0 Reserved ........................................ always reads 0
Offset 70 – Hardware Monitor IRQ Select.....................RW
7-4 Reserved….…… ................................ always reads 0
3-0 HM IRQ Select.….……........................... default = 0
FIR Registers (LDN C)
Offset 30 – Fast IR Activate (00h)................................... RW
7-1 Reserved ........................................always reads 0
0 Fast IR Function ...................................... default = 0
0 Disable................................................... default
1 Enable
Offset 61-60 – FIR I/O Base Address (E800h) ............... RW
15-8 FIR I/O Base.......................................default = E80h
7-0 Reserved ........................................always reads 0
Offset 70 – FIR IRQ Select (00h) .................................... RW
7-4 Reserved ........................................always reads 0
3-0 FIR IRQ Select ......................................... default = 0
Offset 74 – FIR DRQ Select (06h)................................... RW
7-4 Reserved ........................................always reads 0
3-2 FIR DRQ 2 Select................................. default = 01b
1-0 FIR DRQ 1 Select................................. default = 10b
Offset F0 – FIR One DMA Select (00h).......................... RW
7-1 Reserved ........................................always reads 0
0 FIR IRQ Select ......................................... default = 0
ROM Registers (LDN D)
Offset 30 – ROM Interface Activate (01h) ..................... RW
7-1 Reserved ........................................always reads 0
0 ROM Interface
0Disable
1 Enable................................................... default
Offset F0 – ROM Decoding Control (00h) ..................... RW
7 Flash ROM Write Cycles
0 Disable................................................... default
1 Enable
6 FFF00000h–FFF7FFFFh......................... default = 0
5 FFE80000h–FFEFFFFFh........................ default = 0
4 FFE00000h–FFE7FFFFh ........................ default = 0
3 FFD80000h–FFDF0000h .........................default = 0
2 FFD00000h–FFD7FFFFh........................ default = 0
1 FFC80000h–FFCFFFFFh ....................... default = 0
0 FFC00000h–FFC7FFFFh........................ default = 0
Note: ROMCS# is always active for accesses to ISA Memory
FFF80000h – FFFFFFFFh and 000E0000h – 000FFFFFh.