Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -24- Register Descriptions – LDN 1 Parallel Port
Technologies, Inc.
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Parallel Port Registers (LDN 1)
Offset 30 – Parallel Port Activate (03h) ..........................RW
7-2 Reserved ........................................ always reads 0
1-0 Parallel Port Enable….…… ............... default = 11b
00 SPP Mode
01 ECP Mode
10 EPP Mode
11 PIO Disable
Offset 60 – Parallel Port Base Address (DEh) ................RW
7-0 ADR9 ~ ADR2................................... default = 0DEh
If EPP is not enabled, the parallel port can be set to
192 locations, on 4 bytes boundaries form 100h-
3FCh. If EPP is enabled, the parallel port can be set
to 96 locations, on 8 byte boundaries from 100h-
3F8h. In ECP Mode, upper address decode require
A10 active.
Offset 70 – Parallel Port IRQ Select (05h)......................RW
7-4 Reserved ........................................ always reads 0
3-0 Parallel Port IRQ Select.................. default = 0101b
Offset 74 – Parallel Port DRQ Select (02h) ....................RW
7-2 Reserved ........................................ always reads 0
1-0 Parallel Port DRQ Select .................... default = 10b
Offset F0 – Parallel Port Control.................................... RW
7 PS/2 Type Bi-directional Parallel Port Enable
.............................................. default = 0
6 EPP Direction by Register not by IOW . default = 0
5 EPP+ECP….............................................. default = 0
4 EPP Version (0: Ver 1.9)…. .................... default = 0
3 SPP Mode IRQ Polarity…. ..................... default = 0
2-0 Reserved …. ...................................always reads 0