Product specifications

VT1211 LPC SuperIO and Hardware Monitor
Revision 1.0 January 8, 2002 -14- Register Overview
Technologies, Inc.
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REGISTERS
Register Overview
The following tables summarize the configuration and I/O
registers of the VT1211. These tables also document the
power-on default value (“Default”) and access type (“Acc”)
for each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see
individual register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated.
Register Organization
From the Index Port and Data Port Register table, the two
registers can be accessed to enter Configuration mode by
writing a specific value (87h) to Configuration Index Register
twice.
Logical Device Number (LDN) Assignments table shows
that each function block is associated with a Logical Device
Number (LDN). The configuration registers are grouped into
banks, where each bank holds the standard configuration
registers according to its assigned logical device.
Figure presents the standard structure of the configuration
register file. The Super I/O control and configuration
registers are not banked and are only accessed by the Index
Port and Data Port register. The device control and device
configuration registers are duplicated over 14 banks for 14
logical devices. Therefore, by accessing a specific register in
a specific bank is performed by two-step procedure. The
LDN register will first locate the logical device and the Index
register will select the register within that function block.
Configuration Sequence
Accessing a specific device control and device configuration
register can be achieved through three basic steps:
a) Enter configuration mode
b) Configure the chip
c) Escape from configuration mode
Enter Configuration Mode
To place the chip into the configuration mode, two successive
writes of 87h must be applied to Configuration Index Register
2Eh or 4Eh.
Configure the Chip
The Logical Device can be selected from as:
1. Write 07h to Configuration Index Register 2Eh or 4Eh
2. Write the number of the desired logical device to
Configuration Data Register 2Fh or 4Fh
The super I/O configuration registers can be read/write
from/to as:
1. Write index to Configuration Index Register 2Eh or
4Eh
2. Read/write data from/to Configuration Data Register
2Fh or 4Fh
Escape from Configuration Mode
Write AAh to the Configuration Index Register to disable
SuperI/O configuration mode.